head	1.3;
access;
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	pkgsrc-2026Q1:1.3.0.2
	pkgsrc-2026Q1-base:1.3;
locks; strict;
comment	@# @;


1.3
date	2026.03.03.08.19.42;	author adam;	state Exp;
branches;
next	1.2;
commitid	0sUQiqnKM8y1lvwG;

1.2
date	2026.02.17.11.12.06;	author adam;	state Exp;
branches;
next	1.1;
commitid	6Px5G97KSkf3KIuG;

1.1
date	2025.12.25.17.01.49;	author ryoon;	state Exp;
branches;
next	;
commitid	SbM51QyOph9JpOnG;


desc
@@


1.3
log
@py-apycula: updated to 0.30

0.30

Bump Yosys version
Add msgspec to Docker image
Fix examples.
Only push Docker image on push to master
Restructure CI: consolidate chipdb, split examples by board
optimize python packer
Replace pickle with msgspec MessagePack serialization
Speed up CI with ccache for yosys/nextpnr builds
Revert CI to upstream nextpnr
Clean up chipdb generation pipeline
Add a primitive comparison tool.
BUGFIX. Restore PLL routing.
@
text
@# $NetBSD: Makefile,v 1.2 2026/02/17 11:12:06 adam Exp $

DISTNAME=	apycula-0.30
PKGNAME=	${PYPKGPREFIX}-${DISTNAME}
CATEGORIES=	devel python
MASTER_SITES=	${MASTER_SITE_PYPI:=a/apycula/}

MAINTAINER=	ryoon@@NetBSD.org
HOMEPAGE=	https://github.com/YosysHQ/apicula
COMMENT=	Open Source tools for Gowin FPGAs
LICENSE=	mit

TOOL_DEPENDS+=	${PYPKGPREFIX}-setuptools>=78:../../devel/py-setuptools
TOOL_DEPENDS+=	${PYPKGPREFIX}-setuptools_scm-[0-9]*:../../devel/py-setuptools_scm
DEPENDS+=	${PYPKGPREFIX}-crcmod-[0-9]*:../../security/py-crcmod
DEPENDS+=	${PYPKGPREFIX}-msgspec-[0-9]*:../../devel/py-msgspec
DEPENDS+=	${PYPKGPREFIX}-numpy-[0-9]*:../../math/py-numpy

USE_LANGUAGES=	# none

post-install:
.for c in pack pll unpack
	cd ${DESTDIR}${PREFIX}/bin && \
	${MV} gowin_${c} gowin_${c}-${PYVERSSUFFIX} || ${TRUE}
.endfor

.include "../../lang/python/wheel.mk"
.include "../../mk/bsd.pkg.mk"
@


1.2
log
@py-apycula: updated to 0.29

0.29

25A unusual IOs.
Add a description of dedicated pins.
Read information about banks from a DAT file.
Read a list of alt IO functions from a DAT file.
Add IOBUFs for GW5AST-138C
Set fuses for unused I/O
Bump the Yosys version
Fix Tangmega138k overheating
Doc. BSRAM in the GW5A series.
Disable segment gates.
Enable ‘Byte Enable’ on BSRAM. for all chips, including the 5A series.
Add new wire tables.
Set DSP regs defaults
Implement GW5AST-138C clock system.
Add TangMega138k examples.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.1 2025/12/25 17:01:49 ryoon Exp $
d3 1
a3 1
DISTNAME=	apycula-0.29
d13 1
d15 3
a17 1
DEPENDS+=	${PYPKGPREFIX}-crc-[0-9]*:../../devel/py-crc
@


1.1
log
@devel/py-apycula: import py314-apycula-0.28

Open source tools and Documentation for the Gowin FPGA bitstream
format.

Project Apicula uses a combination of fuzzing and parsing of the
vendor data files to provide Python tools for generating bitstreams.
@
text
@d1 1
a1 1
# $NetBSD$
d3 1
a3 1
DISTNAME=	apycula-0.28
@