head 1.3; access; symbols netbsd-11-0-RC5:1.3 netbsd-11-0-RC4:1.3 netbsd-11-0-RC3:1.3 netbsd-11-0-RC2:1.3 netbsd-11-0-RC1:1.3 perseant-exfatfs-base-20250801:1.3 netbsd-11:1.3.0.2 netbsd-11-base:1.3 netbsd-10-1-RELEASE:1.2 perseant-exfatfs-base-20240630:1.2 perseant-exfatfs:1.2.0.6 perseant-exfatfs-base:1.2 netbsd-10-0-RELEASE:1.2 netbsd-10-0-RC6:1.2 netbsd-10-0-RC5:1.2 netbsd-10-0-RC4:1.2 netbsd-10-0-RC3:1.2 netbsd-10-0-RC2:1.2 netbsd-10-0-RC1:1.2 netbsd-10:1.2.0.4 netbsd-10-base:1.2 cjep_sun2x-base1:1.2 cjep_sun2x:1.2.0.2 cjep_sun2x-base:1.2 cjep_staticlib_x-base1:1.2 cjep_staticlib_x:1.1.0.4 cjep_staticlib_x-base:1.1 phil-wifi-20200421:1.1 phil-wifi-20200411:1.1 is-mlppp:1.1.0.2 is-mlppp-base:1.1 phil-wifi-20200406:1.1 phil-wifi-20191119:1.1; locks; strict; comment @# @; 1.3 date 2024.07.02.21.56.00; author mrg; state Exp; branches; next 1.2; commitid wpcIhzmRLvQNijgF; 1.2 date 2021.05.30.01.56.50; author joerg; state Exp; branches 1.2.6.1; next 1.1; commitid 3Zpdqzdbkf2q47VC; 1.1 date 2019.11.11.22.45.03; author joerg; state Exp; branches 1.1.4.1; next ; commitid IMynySmLyNzibuKB; 1.2.6.1 date 2025.08.02.05.20.45; author perseant; state Exp; branches; next ; commitid 23j6GFaDws3O875G; 1.1.4.1 date 2021.05.31.22.10.05; author cjep; state Exp; branches; next ; commitid eWz9SBW0XqKjJlVC; desc @@ 1.3 log @arm64 GCC 12.4 complains about SILateBranchLowering.cpp. turn off stringop-overread warning for GCC. @ text @# $NetBSD: Makefile,v 1.2 2021/05/30 01:56:50 joerg Exp $ LIB= LLVMAMDGPUCodeGen .include CPPFLAGS+= -I${LLVM_SRCDIR}/lib/Target/AMDGPU .PATH: ${LLVM_SRCDIR}/lib/Target/AMDGPU SRCS+= AMDGPUAliasAnalysis.cpp \ AMDGPUAlwaysInlinePass.cpp \ AMDGPUAnnotateKernelFeatures.cpp \ AMDGPUAnnotateUniformValues.cpp \ AMDGPUArgumentUsageInfo.cpp \ AMDGPUAsmPrinter.cpp \ AMDGPUAtomicOptimizer.cpp \ AMDGPUCallLowering.cpp \ AMDGPUCodeGenPrepare.cpp \ AMDGPUExportClustering.cpp \ AMDGPUFixFunctionBitcasts.cpp \ AMDGPUFrameLowering.cpp \ AMDGPUGlobalISelUtils.cpp \ AMDGPUHSAMetadataStreamer.cpp \ AMDGPUInstCombineIntrinsic.cpp \ AMDGPUInstrInfo.cpp \ AMDGPUInstructionSelector.cpp \ AMDGPUISelDAGToDAG.cpp \ AMDGPUISelLowering.cpp \ AMDGPULateCodeGenPrepare.cpp \ AMDGPULegalizerInfo.cpp \ AMDGPULibCalls.cpp \ AMDGPULibFunc.cpp \ AMDGPULowerIntrinsics.cpp \ AMDGPULowerKernelArguments.cpp \ AMDGPULowerKernelAttributes.cpp \ AMDGPULowerModuleLDSPass.cpp \ AMDGPUMachineCFGStructurizer.cpp \ AMDGPUMachineFunction.cpp \ AMDGPUMachineModuleInfo.cpp \ AMDGPUMacroFusion.cpp \ AMDGPUMCInstLower.cpp \ AMDGPUMIRFormatter.cpp \ AMDGPUOpenCLEnqueuedBlockLowering.cpp \ AMDGPUPerfHintAnalysis.cpp \ AMDGPUPostLegalizerCombiner.cpp \ AMDGPUPreLegalizerCombiner.cpp \ AMDGPUPrintfRuntimeBinding.cpp \ AMDGPUPromoteAlloca.cpp \ AMDGPUPropagateAttributes.cpp \ AMDGPURegBankCombiner.cpp \ AMDGPURegisterBankInfo.cpp \ AMDGPURewriteOutArguments.cpp \ AMDGPUSubtarget.cpp \ AMDGPUTargetMachine.cpp \ AMDGPUTargetObjectFile.cpp \ AMDGPUTargetTransformInfo.cpp \ AMDGPUUnifyDivergentExitNodes.cpp \ AMDGPUUnifyMetadata.cpp \ AMDILCFGStructurizer.cpp \ GCNDPPCombine.cpp \ GCNHazardRecognizer.cpp \ GCNILPSched.cpp \ GCNIterativeScheduler.cpp \ GCNMinRegStrategy.cpp \ GCNNSAReassign.cpp \ GCNRegPressure.cpp \ GCNSchedStrategy.cpp \ R600AsmPrinter.cpp \ R600ClauseMergePass.cpp \ R600ControlFlowFinalizer.cpp \ R600EmitClauseMarkers.cpp \ R600ExpandSpecialInstrs.cpp \ R600FrameLowering.cpp \ R600InstrInfo.cpp \ R600ISelLowering.cpp \ R600MachineFunctionInfo.cpp \ R600MachineScheduler.cpp \ R600OpenCLImageTypeLoweringPass.cpp \ R600OptimizeVectorRegisters.cpp \ R600Packetizer.cpp \ R600RegisterInfo.cpp \ SIAnnotateControlFlow.cpp \ SIFixSGPRCopies.cpp \ SIFixVGPRCopies.cpp \ SIFoldOperands.cpp \ SIFormMemoryClauses.cpp \ SIFrameLowering.cpp \ SIInsertHardClauses.cpp \ SIInsertWaitcnts.cpp \ SIInstrInfo.cpp \ SIISelLowering.cpp \ SILateBranchLowering.cpp \ SILoadStoreOptimizer.cpp \ SILowerControlFlow.cpp \ SILowerI1Copies.cpp \ SILowerSGPRSpills.cpp \ SIMachineFunctionInfo.cpp \ SIMachineScheduler.cpp \ SIMemoryLegalizer.cpp \ SIModeRegister.cpp \ SIOptimizeExecMasking.cpp \ SIOptimizeExecMaskingPreRA.cpp \ SIPeepholeSDWA.cpp \ SIPostRABundler.cpp \ SIPreAllocateWWMRegs.cpp \ SIPreEmitPeephole.cpp \ SIProgramInfo.cpp \ SIRegisterInfo.cpp \ SIShrinkInstructions.cpp \ SIWholeQuadMode.cpp TABLEGEN_SRC= AMDGPU.td AMDGPUGISel.td InstCombineTables.td R600.td TABLEGEN_INCLUDES= -I${LLVM_SRCDIR}/lib/Target/AMDGPU TABLEGEN_OUTPUT.AMDGPU.td= \ AMDGPUGenAsmMatcher.inc|-gen-asm-matcher \ AMDGPUGenAsmWriter.inc|-gen-asm-writer \ AMDGPUGenCallingConv.inc|-gen-callingconv \ AMDGPUGenDAGISel.inc|-gen-dag-isel \ AMDGPUGenDisassemblerTables.inc|-gen-disassembler \ AMDGPUGenInstrInfo.inc|-gen-instr-info \ AMDGPUGenMCCodeEmitter.inc|-gen-emitter \ AMDGPUGenMCPseudoLowering.inc|-gen-pseudo-lowering \ AMDGPUGenRegisterBank.inc|-gen-register-bank \ AMDGPUGenRegisterInfo.inc|-gen-register-info \ AMDGPUGenSearchableTables.inc|-gen-searchable-tables \ AMDGPUGenSubtargetInfo.inc|-gen-subtarget TABLEGEN_OUTPUT.InstCombineTables.td= \ InstCombineTables.inc|-gen-searchable-tables TABLEGEN_OUTPUT.AMDGPUGISel.td= \ AMDGPUGenGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPreLegalizerCombinerHelper \ AMDGPUGenGlobalISel.inc|-gen-global-isel \ AMDGPUGenPostLegalizeGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPostLegalizerCombinerHelper \ AMDGPUGenPreLegalizeGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPreLegalizerCombinerHelper \ AMDGPUGenRegBankGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPURegBankCombinerHelper TABLEGEN_OUTPUT.R600.td= \ R600GenAsmWriter.inc|-gen-asm-writer \ R600GenCallingConv.inc|-gen-callingconv \ R600GenDAGISel.inc|-gen-dag-isel \ R600GenDFAPacketizer.inc|-gen-dfa-packetizer \ R600GenInstrInfo.inc|-gen-instr-info \ R600GenMCCodeEmitter.inc|-gen-emitter \ R600GenRegisterInfo.inc|-gen-register-info \ R600GenSubtargetInfo.inc|-gen-subtarget .include "${.PARSEDIR}/../../tablegen.mk" .if defined(HOSTLIB) .include .else .include .endif CWARNFLAGS.gcc+= ${CC_WNO_STRINGOP_OVERREAD} @ 1.2 log @Update LLVM build system for 249b40b558955afe5ac2b549edcf2d7f859c8cc9 This enables the use of modules for a significant build performance gain when building with clang as host compiler or when using HAVE_LLVM=yes. Switch libc++ to using the copy from the mono-repo. @ text @d1 1 a1 1 # $NetBSD: Makefile,v 1.1 2019/11/11 22:45:03 joerg Exp $ d156 2 @ 1.2.6.1 log @Sync with HEAD @ text @d1 1 a1 1 # $NetBSD: Makefile,v 1.3 2024/07/02 21:56:00 mrg Exp $ a155 2 CWARNFLAGS.gcc+= ${CC_WNO_STRINGOP_OVERREAD} @ 1.1 log @Update LLVM to 10.0.0git (01f3a59fb3e2542fce74c768718f594d0debd0da) @ text @d1 1 a1 1 # $NetBSD: Makefile,v 1.1 2019/03/10 12:14:05 mrg Exp $ d20 1 d23 1 d25 1 a25 1 AMDGPUInline.cpp \ d30 1 d37 1 d43 1 d46 2 d51 1 a52 1 AMDGPURegisterInfo.cpp \ a66 1 GCNRegBankReassign.cpp \ a82 1 SIAddIMGInit.cpp \ a84 1 SIFixupVectorISel.cpp \ d89 1 a89 1 SIInsertSkips.cpp \ d93 1 d105 1 d107 2 d113 1 a113 1 TABLEGEN_SRC= AMDGPU.td AMDGPUGISel.td R600.td a121 2 AMDGPUGenIntrinsicEnums.inc|-gen-tgt-intrinsic-enums \ AMDGPUGenIntrinsicImpl.inc|-gen-tgt-intrinsic-impl \ d129 3 d133 5 a137 1 AMDGPUGenGlobalISel.inc|-gen-global-isel @ 1.1.4.1 log @sync with head @ text @d1 1 a1 1 # $NetBSD: Makefile,v 1.2 2021/05/30 01:56:50 joerg Exp $ a19 1 AMDGPUExportClustering.cpp \ a21 1 AMDGPUGlobalISelUtils.cpp \ d23 1 a23 1 AMDGPUInstCombineIntrinsic.cpp \ a27 1 AMDGPULateCodeGenPrepare.cpp \ a33 1 AMDGPULowerModuleLDSPass.cpp \ a38 1 AMDGPUMIRFormatter.cpp \ a40 2 AMDGPUPostLegalizerCombiner.cpp \ AMDGPUPreLegalizerCombiner.cpp \ a43 1 AMDGPURegBankCombiner.cpp \ d45 1 d60 1 d77 1 d80 1 d85 1 a85 1 SIInsertHardClauses.cpp \ a88 1 SILateBranchLowering.cpp \ a99 1 SIPostRABundler.cpp \ a100 2 SIPreEmitPeephole.cpp \ SIProgramInfo.cpp \ d105 1 a105 1 TABLEGEN_SRC= AMDGPU.td AMDGPUGISel.td InstCombineTables.td R600.td d114 2 a122 3 TABLEGEN_OUTPUT.InstCombineTables.td= \ InstCombineTables.inc|-gen-searchable-tables d124 1 a124 5 AMDGPUGenGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPreLegalizerCombinerHelper \ AMDGPUGenGlobalISel.inc|-gen-global-isel \ AMDGPUGenPostLegalizeGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPostLegalizerCombinerHelper \ AMDGPUGenPreLegalizeGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPUPreLegalizerCombinerHelper \ AMDGPUGenRegBankGICombiner.inc|-gen-global-isel-combiner^-combiners=AMDGPURegBankCombinerHelper @