head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.2 netbsd-11-0-RC3:1.1.1.2 gdb-17-1:1.1.1.2 netbsd-11-0-RC2:1.1.1.2 netbsd-11-0-RC1:1.1.1.2 gdb-16-3:1.1.1.2 perseant-exfatfs-base-20250801:1.1.1.2 netbsd-11:1.1.1.2.0.28 netbsd-11-base:1.1.1.2 netbsd-10-1-RELEASE:1.1.1.2 gdb-15-1:1.1.1.2 perseant-exfatfs-base-20240630:1.1.1.2 perseant-exfatfs:1.1.1.2.0.26 perseant-exfatfs-base:1.1.1.2 netbsd-8-3-RELEASE:1.1.1.2 netbsd-9-4-RELEASE:1.1.1.2 netbsd-10-0-RELEASE:1.1.1.2 netbsd-10-0-RC6:1.1.1.2 netbsd-10-0-RC5:1.1.1.2 netbsd-10-0-RC4:1.1.1.2 netbsd-10-0-RC3:1.1.1.2 netbsd-10-0-RC2:1.1.1.2 netbsd-10-0-RC1:1.1.1.2 gdb-13-2:1.1.1.2 netbsd-10:1.1.1.2.0.24 netbsd-10-base:1.1.1.2 netbsd-9-3-RELEASE:1.1.1.2 cjep_sun2x-base1:1.1.1.2 cjep_sun2x:1.1.1.2.0.22 cjep_sun2x-base:1.1.1.2 cjep_staticlib_x-base1:1.1.1.2 netbsd-9-2-RELEASE:1.1.1.2 cjep_staticlib_x:1.1.1.2.0.20 cjep_staticlib_x-base:1.1.1.2 netbsd-9-1-RELEASE:1.1.1.2 GDB-11-0-50-20200914-git:1.1.1.2 phil-wifi-20200421:1.1.1.2 phil-wifi-20200411:1.1.1.2 is-mlppp:1.1.1.2.0.18 is-mlppp-base:1.1.1.2 phil-wifi-20200406:1.1.1.2 netbsd-8-2-RELEASE:1.1.1.2 netbsd-9-0-RELEASE:1.1.1.2 netbsd-9-0-RC2:1.1.1.2 netbsd-9-0-RC1:1.1.1.2 phil-wifi-20191119:1.1.1.2 netbsd-9:1.1.1.2.0.16 netbsd-9-base:1.1.1.2 phil-wifi-20190609:1.1.1.2 netbsd-8-1-RELEASE:1.1.1.2 gdb-8-3:1.1.1.2 netbsd-8-1-RC1:1.1.1.2 pgoyette-compat-merge-20190127:1.1.1.2 pgoyette-compat-20190127:1.1.1.2 pgoyette-compat-20190118:1.1.1.2 pgoyette-compat-1226:1.1.1.2 pgoyette-compat-1126:1.1.1.2 pgoyette-compat-1020:1.1.1.2 pgoyette-compat-0930:1.1.1.2 pgoyette-compat-0906:1.1.1.2 netbsd-7-2-RELEASE:1.1.1.1 pgoyette-compat-0728:1.1.1.2 netbsd-8-0-RELEASE:1.1.1.2 phil-wifi:1.1.1.2.0.14 phil-wifi-base:1.1.1.2 pgoyette-compat-0625:1.1.1.2 netbsd-8-0-RC2:1.1.1.2 pgoyette-compat-0521:1.1.1.2 pgoyette-compat-0502:1.1.1.2 pgoyette-compat-0422:1.1.1.2 netbsd-8-0-RC1:1.1.1.2 pgoyette-compat-0415:1.1.1.2 pgoyette-compat-0407:1.1.1.2 pgoyette-compat-0330:1.1.1.2 pgoyette-compat-0322:1.1.1.2 pgoyette-compat-0315:1.1.1.2 netbsd-7-1-2-RELEASE:1.1.1.1 pgoyette-compat:1.1.1.2.0.12 pgoyette-compat-base:1.1.1.2 netbsd-7-1-1-RELEASE:1.1.1.1 gdb-8-0-1:1.1.1.2 matt-nb8-mediatek:1.1.1.2.0.10 matt-nb8-mediatek-base:1.1.1.2 perseant-stdc-iso10646:1.1.1.2.0.8 perseant-stdc-iso10646-base:1.1.1.2 netbsd-8:1.1.1.2.0.6 netbsd-8-base:1.1.1.2 prg-localcount2-base3:1.1.1.2 prg-localcount2-base2:1.1.1.2 prg-localcount2-base1:1.1.1.2 prg-localcount2:1.1.1.2.0.4 prg-localcount2-base:1.1.1.2 pgoyette-localcount-20170426:1.1.1.2 bouyer-socketcan-base1:1.1.1.2 pgoyette-localcount-20170320:1.1.1.2 netbsd-7-1:1.1.1.1.0.16 netbsd-7-1-RELEASE:1.1.1.1 netbsd-7-1-RC2:1.1.1.1 netbsd-7-nhusb-base-20170116:1.1.1.1 bouyer-socketcan:1.1.1.2.0.2 bouyer-socketcan-base:1.1.1.2 pgoyette-localcount-20170107:1.1.1.2 netbsd-7-1-RC1:1.1.1.1 pgoyette-localcount-20161104:1.1.1.2 netbsd-7-0-2-RELEASE:1.1.1.1 gdb-7-12:1.1.1.2 localcount-20160914:1.1.1.1 netbsd-7-nhusb:1.1.1.1.0.14 netbsd-7-nhusb-base:1.1.1.1 pgoyette-localcount-20160806:1.1.1.1 pgoyette-localcount-20160726:1.1.1.1 pgoyette-localcount:1.1.1.1.0.12 pgoyette-localcount-base:1.1.1.1 netbsd-7-0-1-RELEASE:1.1.1.1 gdb-7-10-1:1.1.1.1 netbsd-7-0:1.1.1.1.0.10 netbsd-7-0-RELEASE:1.1.1.1 gdb-7-9-1:1.1.1.1 netbsd-7-0-RC3:1.1.1.1 netbsd-7-0-RC2:1.1.1.1 netbsd-7-0-RC1:1.1.1.1 tls-maxphys-base:1.1.1.1 tls-maxphys:1.1.1.1.0.8 netbsd-7:1.1.1.1.0.6 netbsd-7-base:1.1.1.1 gdb-7-7-1:1.1.1.1 yamt-pagecache:1.1.1.1.0.4 yamt-pagecache-base9:1.1.1.1 tls-earlyentropy:1.1.1.1.0.2 tls-earlyentropy-base:1.1.1.1 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.1 riastradh-drm2-base3:1.1.1.1 gdb-7-6-1:1.1.1.1 FSF:1.1.1; locks; strict; comment @# @; 1.1 date 2013.10.03.15.44.20; author christos; state Exp; branches 1.1.1.1; next ; commitid m91IYDmHTME7wR7x; 1.1.1.1 date 2013.10.03.15.44.20; author christos; state Exp; branches 1.1.1.1.4.1 1.1.1.1.8.1 1.1.1.1.12.1; next 1.1.1.2; commitid m91IYDmHTME7wR7x; 1.1.1.2 date 2016.10.12.16.47.10; author christos; state Exp; branches; next ; commitid WncVqozyBBQMmSpz; 1.1.1.1.4.1 date 2013.10.03.15.44.20; author yamt; state dead; branches; next 1.1.1.1.4.2; commitid SRuOnF9k1i4dcyBx; 1.1.1.1.4.2 date 2014.05.22.16.00.32; author yamt; state Exp; branches; next ; commitid SRuOnF9k1i4dcyBx; 1.1.1.1.8.1 date 2013.10.03.15.44.20; author tls; state dead; branches; next 1.1.1.1.8.2; commitid jTnpym9Qu0o4R1Nx; 1.1.1.1.8.2 date 2014.08.19.23.58.38; author tls; state Exp; branches; next ; commitid jTnpym9Qu0o4R1Nx; 1.1.1.1.12.1 date 2016.11.04.14.46.48; author pgoyette; state Exp; branches; next ; commitid 2m1JRwYmpwPkOOsz; desc @@ 1.1 log @Initial revision @ text @/* Adapteva epiphany opcode support. -*- C -*- Copyright 2009, 2011 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of the GNU Binutils and of GDB. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* Each section is delimited with start and end markers. -opc.h additions use: "-- opc.h" -opc.c additions use: "-- opc.c" -asm.c additions use: "-- asm.c" -dis.c additions use: "-- dis.c" -ibd.h additions use: "-- ibd.h". */ /* -- opc.h */ /* enumerate relaxation types for gas. */ typedef enum epiphany_relax_types { EPIPHANY_RELAX_NONE=0, EPIPHANY_RELAX_NEED_RELAXING, EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */ EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b +-2*16 */ EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */ EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */ EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */ EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */ EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */ EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */ } EPIPHANY_RELAX_TYPES; /* Override disassembly hashing... */ /* Can only depend on instruction having 4 decode bits which gets us to the major groups of 16/32 instructions. */ #undef CGEN_DIS_HASH_SIZE #if 1 /* hash code on the 4 LSBs */ #define CGEN_DIS_HASH_SIZE 16 #define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf) #else #define CGEN_DIS_HASH_SIZE 1 #define CGEN_DIS_HASH(buf, value) 0 #endif extern const char * parse_shortregs (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD * keywords, long * valuep); extern const char * parse_branch_addr (CGEN_CPU_DESC cd, const char ** strp, int opindex, int opinfo, enum cgen_parse_operand_result * resultp, bfd_vma *valuep); /* Allows reason codes to be output when assembler errors occur. */ #define CGEN_VERBOSE_ASSEMBLER_ERRORS /* -- opc.c */ /* -- asm.c */ const char * parse_shortregs (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD * keywords, long * regno) { const char * errmsg; /* Parse register. */ errmsg = cgen_parse_keyword (cd, strp, keywords, regno); if (errmsg) return errmsg; if (*regno > 7) errmsg = _("register unavailable for short instructions"); return errmsg; } static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int, long *); static const char * parse_uimm_not_reg (CGEN_CPU_DESC cd, const char ** strp, int opindex, unsigned long * valuep) { long * svalp = (void *) valuep; return parse_simm_not_reg (cd, strp, opindex, svalp); } /* Handle simm3/simm11/imm3/imm12. */ static const char * parse_simm_not_reg (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) { const char * errmsg; int sign = 0; int bits = 0; switch (opindex) { case EPIPHANY_OPERAND_SIMM3: sign = 1; bits = 3; break; case EPIPHANY_OPERAND_SIMM11: sign = 1; bits = 11; break; case EPIPHANY_OPERAND_DISP3: sign = 0; bits = 3; break; case EPIPHANY_OPERAND_DISP11: /* Load/store displacement is a sign-magnitude 12 bit value. */ sign = 0; bits = 11; break; } /* First try to parse as a register name and reject the operand. */ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep); if (!errmsg) return _("register name used as immediate value"); errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep) : cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep)); if (errmsg) return errmsg; if (sign) errmsg = cgen_validate_signed_integer (*valuep, -((1L << bits) - 1), (1 << (bits - 1)) - 1); else errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1); return errmsg; } static const char * parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char ** strp, int opindex ATTRIBUTE_UNUSED, unsigned long *valuep) { if (**strp == '#') ++*strp; /* Skip leading hashes. */ if (**strp == '-') { *valuep = 1; ++*strp; } else if (**strp == '+') { *valuep = 0; ++*strp; } else *valuep = 0; return NULL; } static const char * parse_imm8 (CGEN_CPU_DESC cd, const char ** strp, int opindex, bfd_reloc_code_real_type code, enum cgen_parse_operand_result * result_type, bfd_vma * valuep) { const char * errmsg; enum cgen_parse_operand_result rt; long dummyval; if (!result_type) result_type = &rt; code = BFD_RELOC_NONE; if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, &dummyval)) /* Don't treat "mov ip,ip" as a move-immediate. */ return _("register source in immediate move"); errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep); if (errmsg) return errmsg; if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff); else errmsg = _("byte relocation unsupported"); *valuep &= 0xff; return errmsg; } static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'"); static const char * parse_imm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, bfd_reloc_code_real_type code ATTRIBUTE_UNUSED, enum cgen_parse_operand_result * result_type, bfd_vma * valuep) { const char * errmsg; enum cgen_parse_operand_result rt; long dummyval; if (!result_type) result_type = &rt; if (strncasecmp (*strp, "%high(", 6) == 0) { *strp += 6; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH, result_type, valuep); if (**strp != ')') return MISSING_CLOSE_PARENTHESIS; ++*strp; *valuep >>= 16; } else if (strncasecmp (*strp, "%low(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW, result_type, valuep); if (**strp != ')') return MISSING_CLOSE_PARENTHESIS; ++*strp; } else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, &dummyval)) /* Don't treat "mov ip,ip" as a move-immediate. */ return _("register source in immediate move"); else errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16, result_type, valuep); if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff); *valuep &= 0xffff; return errmsg; } const char * parse_branch_addr (CGEN_CPU_DESC cd, const char ** strp, int opindex, int opinfo ATTRIBUTE_UNUSED, enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED, bfd_vma *valuep ATTRIBUTE_UNUSED) { const char * errmsg; enum cgen_parse_operand_result result_type; bfd_reloc_code_real_type code = BFD_RELOC_NONE; bfd_vma value; switch (opindex) { case EPIPHANY_OPERAND_SIMM24: code = BFD_RELOC_EPIPHANY_SIMM24; break; case EPIPHANY_OPERAND_SIMM8: code = BFD_RELOC_EPIPHANY_SIMM8; break; default: errmsg = _("ABORT: unknown operand"); return errmsg; } errmsg = cgen_parse_address (cd, strp, opindex, code, &result_type, &value); if (errmsg == NULL) { if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { /* Act as if we had done a PC-relative branch, ala .+num. */ char buf[20]; const char * bufp = (const char *) buf; sprintf (buf, ".+%ld", (long) value); errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type, &value); } if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) { /* This will happen for things like (s2-s1) where s2 and s1 are labels. */ /* Nothing further to be done. */ } else errmsg = _("Not a pc-relative address."); } return errmsg; } /* -- dis.c */ #define CGEN_PRINT_INSN epiphany_print_insn static int epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { bfd_byte buf[CGEN_MAX_INSN_SIZE]; int buflen; int status; info->bytes_per_chunk = 2; /* Attempt to read the base part of the insn. */ info->bytes_per_line = buflen = cd->base_insn_bitsize / 8; status = (*info->read_memory_func) (pc, buf, buflen, info); /* Try again with the minimum part, if min < base. */ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) { info->bytes_per_line = buflen = cd->min_insn_bitsize / 8; status = (*info->read_memory_func) (pc, buf, buflen, info); } if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } return print_insn (cd, pc, info, buf, buflen); } static void print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, value ? "-" : "+"); } static void print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { print_address (cd, dis_info, value, attrs, pc, length); } static void print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, unsigned long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *)dis_info; if (value & 0x800) (*info->fprintf_func) (info->stream, "-"); value &= 0x7ff; print_address (cd, dis_info, value, attrs, pc, length); } /* -- */ @ 1.1.1.1 log @Import gdb 7.6.1 News from: http://sourceware.org/gdb/news: August 30th, 2013: GDB 7.6.1 Released! The latest version of GDB, version 7.6.1, is available for download. This is a minor corrective release over GDB 7.6, fixing the following issues: PR tdep/15420 (Cannot debug threaded programs on newer versions of x86-solaris - Solaris 10, Update 10 or later) PR remote/15455 (QTro remote packet broken) PR build/15476 (Build failure due to incomplete enum type in utils.h) PR server/15594 (tls support in 64x32 x86 gdbserver doesn't extend address to 64 bit) PR server/15075 (dprintf inteferes with "next") PR server/15434 (dprintf uses a synchronous 'continue' even in non-stop mode) PR tui/14880 (In split register layouts, up results in assertion failure in value.c) PR c++/15519 (GDB 7.6 is 94x slower than GDB 7.5.1 using a certain core file) PR gdb/15837 (GDB prints entry values for local variables) PR gdb/15415 (gdb resolves symbolic links when passing argv[0]) PR cli/15603 (CTRL-C can no longer interrupt inferior) PR gdb/15604 (gdbserver socket leak 7.5 regression) April 26th, 2013: GDB 7.6 Released! The latest version of GDB, version 7.6, is available for download. Changes in this release include: New native configurations (ARM AArch64 GNU/Linux, FreeBSD/powerpc, 86_64/Cygwin and Tilera TILE-Gx GNU/Linux) New target configurations (ARM AArch64, ARM AArch64 GNU/Linux, Lynx 178 PowerPC, x86_64/Cygwin, and Tilera TILE-Gx GNU/Linux) Support for the "mini debuginfo" section, .gnu_debugdata The C++ ABI now defaults to the GNU v3 ABI More Python scripting improvements Some GDB/MI improvements New configure options, new commands, and options New remote packets A new "target record-btrace" has been added while the "target record" command has been renamed to "target record-full" See the NEWS file for a more complete and detailed list of what this release includes. March 12th, 2013: GDB 7.6 branch created The GDB 7.6 branch (gdb_7_6-branch) has been created. To check out a copy of the branch use: cvs -d :pserver:anoncvs@@sourceware.org:/cvs/src co -r gdb_7_6-branch gdb November 29th, 2012: GDB 7.5.1 Released! The latest version of GDB, version 7.5.1, is available for download. This is a minor corrective release over GDB 7.5, fixing the following issues: An "Attempt to dereference a generic pointer" errors (-var-create). Backtrace problems on x32 (PR backtrace/14646). next/step/finish problems on x32 (PR gdb/14647). A "malformed linespec error: unexpected keyword, [...]" error (PR breakpoints/14643). GDB crash while stepping through powerpc (32bits) code. A failed assertion in linux_ptrace_test_ret_to_nx. A "!frame_id_inlined_p (frame_id)" failed assertion. A "No more reverse-execution history." error during reverse "next" execution (PR 14548). Incomplete command descriptions in "apropos" output. PR gdb/14494 (a GDB crash difficult to characterize). Various build warnings. August 17th, 2012: GDB 7.5 Released! The latest version of GDB, version 7.5, is available for download. Changes in this release include: Go language support. New targets (x32 ABI, microMIPS, Renesas RL78, HP OpenVMS ia64). More Python scripting improvements. SDT (Static Defined Tracing) probes support with SystemTap probes. GDBserver improvements (stdio connections, target-side evaluation of breakpoint conditions, remote protocol improvements). Other miscellaneous improvements (ability to stop when a shared library is loaded/unloaded, dynamic printf, etc). Reverse debugging on ARM. The binary "gdbtui" has been abandoned and can no longer be built. Use "gdb -tui" instead. See the NEWS file for a more complete and detailed list of what this release includes. July 17th, 2012: GDB 7.5 branch created The GDB 7.5 branch (gdb_7_5-branch) has been created. To check out a copy of the branch use: cvs -d :pserver:anoncvs@@sourceware.org:/cvs/src co -r gdb_7_5-branch gdb April 26th, 2012: GDB 7.4.1 Released! The latest version of GDB, version 7.4.1, is available for download. This is a minor corrective release over GDB 7.4, fixing the following issues: [GDB/MI] Error when resuming program execution in all-stop mode ("Cannot execute this command without a live selected thread"). [Pascal] Polluted display of class methods parameters. [target remote] Errror when connecting to remote target where disconnected tracing is in effect. [AVX] Float and ymm* register values not available. [GDB] Crash when using the "finish" command. [build] makeinfo should not be required to build GDB. January 24th, 2012: GDB 7.4 Released! The latest version of GDB, version 7.4, is available for download. Changes in this release include: Many Python scripting improvements Better support for ambiguous linespecs Masked watchpoints Tracepoint support improvements Support for Texas Instruments TMS320C6x (tic6x-*-*) A Renesas RL78 simulator (rl78-*-elf) Some minor Remote protocol extensions and GDB/MI changes See the NEWS file for a more complete and detailed list of what this release includes. Note that the gdbtui binary is deprecated, starting with GDB 7.5. Use "gdb -tui" instead. January 9, 2012: Extensibility support using Guile GDB ought to support extensibility using Guile, the GNU extensibility package (an implementation of Scheme). We are looking for people to write the code to interface the two. Please write to gdb-patches AT sourceware DOT org if you are interested. December 13, 2011: GDB 7.4 branch created The GDB 7.4 branch (gdb_7_4-branch) has been created. To check out a copy of the branch use: cvs -d :pserver:anoncvs@@sourceware.org:/cvs/src co -r gdb_7_4-branch gdb September 30, 2011: Release Mistakes in GDB Versions 6.0 - 7.3 A mistake has been detected in the release tar files for all GDB releases from version 6.0 to version 7.3 (included). The mistake has been corrected, and the FSF issued the following announcements: Making up for a release mistake in GDB versions 6.0 - 6.6 Making up for a release mistake in GDB versions 6.7 - 7.3 @ text @@ 1.1.1.1.12.1 log @Sync with HEAD @ text @a351 1 info->bytes_per_line = 4; d354 1 a354 1 buflen = cd->base_insn_bitsize / 8; d360 1 a360 1 buflen = cd->min_insn_bitsize / 8; @ 1.1.1.2 log @import gdb-7.12 @ text @a351 1 info->bytes_per_line = 4; d354 1 a354 1 buflen = cd->base_insn_bitsize / 8; d360 1 a360 1 buflen = cd->min_insn_bitsize / 8; @ 1.1.1.1.8.1 log @file epiphany.opc was added on branch tls-maxphys on 2014-08-19 23:58:38 +0000 @ text @d1 416 @ 1.1.1.1.8.2 log @Rebase to HEAD as of a few days ago. @ text @a0 416 /* Adapteva epiphany opcode support. -*- C -*- Copyright 2009, 2011 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of the GNU Binutils and of GDB. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* Each section is delimited with start and end markers. -opc.h additions use: "-- opc.h" -opc.c additions use: "-- opc.c" -asm.c additions use: "-- asm.c" -dis.c additions use: "-- dis.c" -ibd.h additions use: "-- ibd.h". */ /* -- opc.h */ /* enumerate relaxation types for gas. */ typedef enum epiphany_relax_types { EPIPHANY_RELAX_NONE=0, EPIPHANY_RELAX_NEED_RELAXING, EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */ EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b +-2*16 */ EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */ EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */ EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */ EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */ EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */ EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */ } EPIPHANY_RELAX_TYPES; /* Override disassembly hashing... */ /* Can only depend on instruction having 4 decode bits which gets us to the major groups of 16/32 instructions. */ #undef CGEN_DIS_HASH_SIZE #if 1 /* hash code on the 4 LSBs */ #define CGEN_DIS_HASH_SIZE 16 #define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf) #else #define CGEN_DIS_HASH_SIZE 1 #define CGEN_DIS_HASH(buf, value) 0 #endif extern const char * parse_shortregs (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD * keywords, long * valuep); extern const char * parse_branch_addr (CGEN_CPU_DESC cd, const char ** strp, int opindex, int opinfo, enum cgen_parse_operand_result * resultp, bfd_vma *valuep); /* Allows reason codes to be output when assembler errors occur. */ #define CGEN_VERBOSE_ASSEMBLER_ERRORS /* -- opc.c */ /* -- asm.c */ const char * parse_shortregs (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD * keywords, long * regno) { const char * errmsg; /* Parse register. */ errmsg = cgen_parse_keyword (cd, strp, keywords, regno); if (errmsg) return errmsg; if (*regno > 7) errmsg = _("register unavailable for short instructions"); return errmsg; } static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int, long *); static const char * parse_uimm_not_reg (CGEN_CPU_DESC cd, const char ** strp, int opindex, unsigned long * valuep) { long * svalp = (void *) valuep; return parse_simm_not_reg (cd, strp, opindex, svalp); } /* Handle simm3/simm11/imm3/imm12. */ static const char * parse_simm_not_reg (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) { const char * errmsg; int sign = 0; int bits = 0; switch (opindex) { case EPIPHANY_OPERAND_SIMM3: sign = 1; bits = 3; break; case EPIPHANY_OPERAND_SIMM11: sign = 1; bits = 11; break; case EPIPHANY_OPERAND_DISP3: sign = 0; bits = 3; break; case EPIPHANY_OPERAND_DISP11: /* Load/store displacement is a sign-magnitude 12 bit value. */ sign = 0; bits = 11; break; } /* First try to parse as a register name and reject the operand. */ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep); if (!errmsg) return _("register name used as immediate value"); errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep) : cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep)); if (errmsg) return errmsg; if (sign) errmsg = cgen_validate_signed_integer (*valuep, -((1L << bits) - 1), (1 << (bits - 1)) - 1); else errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1); return errmsg; } static const char * parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char ** strp, int opindex ATTRIBUTE_UNUSED, unsigned long *valuep) { if (**strp == '#') ++*strp; /* Skip leading hashes. */ if (**strp == '-') { *valuep = 1; ++*strp; } else if (**strp == '+') { *valuep = 0; ++*strp; } else *valuep = 0; return NULL; } static const char * parse_imm8 (CGEN_CPU_DESC cd, const char ** strp, int opindex, bfd_reloc_code_real_type code, enum cgen_parse_operand_result * result_type, bfd_vma * valuep) { const char * errmsg; enum cgen_parse_operand_result rt; long dummyval; if (!result_type) result_type = &rt; code = BFD_RELOC_NONE; if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, &dummyval)) /* Don't treat "mov ip,ip" as a move-immediate. */ return _("register source in immediate move"); errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep); if (errmsg) return errmsg; if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff); else errmsg = _("byte relocation unsupported"); *valuep &= 0xff; return errmsg; } static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'"); static const char * parse_imm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, bfd_reloc_code_real_type code ATTRIBUTE_UNUSED, enum cgen_parse_operand_result * result_type, bfd_vma * valuep) { const char * errmsg; enum cgen_parse_operand_result rt; long dummyval; if (!result_type) result_type = &rt; if (strncasecmp (*strp, "%high(", 6) == 0) { *strp += 6; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH, result_type, valuep); if (**strp != ')') return MISSING_CLOSE_PARENTHESIS; ++*strp; *valuep >>= 16; } else if (strncasecmp (*strp, "%low(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW, result_type, valuep); if (**strp != ')') return MISSING_CLOSE_PARENTHESIS; ++*strp; } else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, &dummyval)) /* Don't treat "mov ip,ip" as a move-immediate. */ return _("register source in immediate move"); else errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16, result_type, valuep); if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff); *valuep &= 0xffff; return errmsg; } const char * parse_branch_addr (CGEN_CPU_DESC cd, const char ** strp, int opindex, int opinfo ATTRIBUTE_UNUSED, enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED, bfd_vma *valuep ATTRIBUTE_UNUSED) { const char * errmsg; enum cgen_parse_operand_result result_type; bfd_reloc_code_real_type code = BFD_RELOC_NONE; bfd_vma value; switch (opindex) { case EPIPHANY_OPERAND_SIMM24: code = BFD_RELOC_EPIPHANY_SIMM24; break; case EPIPHANY_OPERAND_SIMM8: code = BFD_RELOC_EPIPHANY_SIMM8; break; default: errmsg = _("ABORT: unknown operand"); return errmsg; } errmsg = cgen_parse_address (cd, strp, opindex, code, &result_type, &value); if (errmsg == NULL) { if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { /* Act as if we had done a PC-relative branch, ala .+num. */ char buf[20]; const char * bufp = (const char *) buf; sprintf (buf, ".+%ld", (long) value); errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type, &value); } if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) { /* This will happen for things like (s2-s1) where s2 and s1 are labels. */ /* Nothing further to be done. */ } else errmsg = _("Not a pc-relative address."); } return errmsg; } /* -- dis.c */ #define CGEN_PRINT_INSN epiphany_print_insn static int epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { bfd_byte buf[CGEN_MAX_INSN_SIZE]; int buflen; int status; info->bytes_per_chunk = 2; /* Attempt to read the base part of the insn. */ info->bytes_per_line = buflen = cd->base_insn_bitsize / 8; status = (*info->read_memory_func) (pc, buf, buflen, info); /* Try again with the minimum part, if min < base. */ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) { info->bytes_per_line = buflen = cd->min_insn_bitsize / 8; status = (*info->read_memory_func) (pc, buf, buflen, info); } if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } return print_insn (cd, pc, info, buf, buflen); } static void print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, value ? "-" : "+"); } static void print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { print_address (cd, dis_info, value, attrs, pc, length); } static void print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, unsigned long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *)dis_info; if (value & 0x800) (*info->fprintf_func) (info->stream, "-"); value &= 0x7ff; print_address (cd, dis_info, value, attrs, pc, length); } /* -- */ @ 1.1.1.1.4.1 log @file epiphany.opc was added on branch yamt-pagecache on 2014-05-22 16:00:32 +0000 @ text @d1 416 @ 1.1.1.1.4.2 log @sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments") @ text @a0 416 /* Adapteva epiphany opcode support. -*- C -*- Copyright 2009, 2011 Free Software Foundation, Inc. Contributed by Embecosm on behalf of Adapteva, Inc. This file is part of the GNU Binutils and of GDB. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* Each section is delimited with start and end markers. -opc.h additions use: "-- opc.h" -opc.c additions use: "-- opc.c" -asm.c additions use: "-- asm.c" -dis.c additions use: "-- dis.c" -ibd.h additions use: "-- ibd.h". */ /* -- opc.h */ /* enumerate relaxation types for gas. */ typedef enum epiphany_relax_types { EPIPHANY_RELAX_NONE=0, EPIPHANY_RELAX_NEED_RELAXING, EPIPHANY_RELAX_BRANCH_SHORT, /* Fits into +127..-128 */ EPIPHANY_RELAX_BRANCH_LONG, /* b/bl/b +-2*16 */ EPIPHANY_RELAX_ARITH_SIMM3, /* add/sub -7..3 */ EPIPHANY_RELAX_ARITH_SIMM11, /* add/sub -2**11-1 .. 2**10-1 */ EPIPHANY_RELAX_MOV_IMM8, /* mov r,imm8 */ EPIPHANY_RELAX_MOV_IMM16, /* mov r,imm16 */ EPIPHANY_RELAX_LDST_IMM3, /* (ldr|str)* r,[r,disp3] */ EPIPHANY_RELAX_LDST_IMM11 /* (ldr|str)* r,[r,disp11] */ } EPIPHANY_RELAX_TYPES; /* Override disassembly hashing... */ /* Can only depend on instruction having 4 decode bits which gets us to the major groups of 16/32 instructions. */ #undef CGEN_DIS_HASH_SIZE #if 1 /* hash code on the 4 LSBs */ #define CGEN_DIS_HASH_SIZE 16 #define CGEN_DIS_HASH(buf, value) ((*buf) & 0xf) #else #define CGEN_DIS_HASH_SIZE 1 #define CGEN_DIS_HASH(buf, value) 0 #endif extern const char * parse_shortregs (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD * keywords, long * valuep); extern const char * parse_branch_addr (CGEN_CPU_DESC cd, const char ** strp, int opindex, int opinfo, enum cgen_parse_operand_result * resultp, bfd_vma *valuep); /* Allows reason codes to be output when assembler errors occur. */ #define CGEN_VERBOSE_ASSEMBLER_ERRORS /* -- opc.c */ /* -- asm.c */ const char * parse_shortregs (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD * keywords, long * regno) { const char * errmsg; /* Parse register. */ errmsg = cgen_parse_keyword (cd, strp, keywords, regno); if (errmsg) return errmsg; if (*regno > 7) errmsg = _("register unavailable for short instructions"); return errmsg; } static const char * parse_simm_not_reg (CGEN_CPU_DESC, const char **, int, long *); static const char * parse_uimm_not_reg (CGEN_CPU_DESC cd, const char ** strp, int opindex, unsigned long * valuep) { long * svalp = (void *) valuep; return parse_simm_not_reg (cd, strp, opindex, svalp); } /* Handle simm3/simm11/imm3/imm12. */ static const char * parse_simm_not_reg (CGEN_CPU_DESC cd, const char ** strp, int opindex, long * valuep) { const char * errmsg; int sign = 0; int bits = 0; switch (opindex) { case EPIPHANY_OPERAND_SIMM3: sign = 1; bits = 3; break; case EPIPHANY_OPERAND_SIMM11: sign = 1; bits = 11; break; case EPIPHANY_OPERAND_DISP3: sign = 0; bits = 3; break; case EPIPHANY_OPERAND_DISP11: /* Load/store displacement is a sign-magnitude 12 bit value. */ sign = 0; bits = 11; break; } /* First try to parse as a register name and reject the operand. */ errmsg = cgen_parse_keyword (cd, strp, & epiphany_cgen_opval_gr_names,valuep); if (!errmsg) return _("register name used as immediate value"); errmsg = (sign ? cgen_parse_signed_integer (cd, strp, opindex, valuep) : cgen_parse_unsigned_integer (cd, strp, opindex, (unsigned long *) valuep)); if (errmsg) return errmsg; if (sign) errmsg = cgen_validate_signed_integer (*valuep, -((1L << bits) - 1), (1 << (bits - 1)) - 1); else errmsg = cgen_validate_unsigned_integer (*valuep, 0, (1L << bits) - 1); return errmsg; } static const char * parse_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, const char ** strp, int opindex ATTRIBUTE_UNUSED, unsigned long *valuep) { if (**strp == '#') ++*strp; /* Skip leading hashes. */ if (**strp == '-') { *valuep = 1; ++*strp; } else if (**strp == '+') { *valuep = 0; ++*strp; } else *valuep = 0; return NULL; } static const char * parse_imm8 (CGEN_CPU_DESC cd, const char ** strp, int opindex, bfd_reloc_code_real_type code, enum cgen_parse_operand_result * result_type, bfd_vma * valuep) { const char * errmsg; enum cgen_parse_operand_result rt; long dummyval; if (!result_type) result_type = &rt; code = BFD_RELOC_NONE; if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, &dummyval)) /* Don't treat "mov ip,ip" as a move-immediate. */ return _("register source in immediate move"); errmsg = cgen_parse_address (cd, strp, opindex, code, result_type, valuep); if (errmsg) return errmsg; if (*result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xff); else errmsg = _("byte relocation unsupported"); *valuep &= 0xff; return errmsg; } static const char * MISSING_CLOSE_PARENTHESIS = N_("missing `)'"); static const char * parse_imm16 (CGEN_CPU_DESC cd, const char ** strp, int opindex, bfd_reloc_code_real_type code ATTRIBUTE_UNUSED, enum cgen_parse_operand_result * result_type, bfd_vma * valuep) { const char * errmsg; enum cgen_parse_operand_result rt; long dummyval; if (!result_type) result_type = &rt; if (strncasecmp (*strp, "%high(", 6) == 0) { *strp += 6; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_HIGH, result_type, valuep); if (**strp != ')') return MISSING_CLOSE_PARENTHESIS; ++*strp; *valuep >>= 16; } else if (strncasecmp (*strp, "%low(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_EPIPHANY_LOW, result_type, valuep); if (**strp != ')') return MISSING_CLOSE_PARENTHESIS; ++*strp; } else if (!cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_gr_names, &dummyval) || !cgen_parse_keyword (cd, strp, &epiphany_cgen_opval_cr_names, &dummyval)) /* Don't treat "mov ip,ip" as a move-immediate. */ return _("register source in immediate move"); else errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_16, result_type, valuep); if (!errmsg && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) errmsg = cgen_validate_unsigned_integer (*valuep, 0, 0xffff); *valuep &= 0xffff; return errmsg; } const char * parse_branch_addr (CGEN_CPU_DESC cd, const char ** strp, int opindex, int opinfo ATTRIBUTE_UNUSED, enum cgen_parse_operand_result * resultp ATTRIBUTE_UNUSED, bfd_vma *valuep ATTRIBUTE_UNUSED) { const char * errmsg; enum cgen_parse_operand_result result_type; bfd_reloc_code_real_type code = BFD_RELOC_NONE; bfd_vma value; switch (opindex) { case EPIPHANY_OPERAND_SIMM24: code = BFD_RELOC_EPIPHANY_SIMM24; break; case EPIPHANY_OPERAND_SIMM8: code = BFD_RELOC_EPIPHANY_SIMM8; break; default: errmsg = _("ABORT: unknown operand"); return errmsg; } errmsg = cgen_parse_address (cd, strp, opindex, code, &result_type, &value); if (errmsg == NULL) { if (result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { /* Act as if we had done a PC-relative branch, ala .+num. */ char buf[20]; const char * bufp = (const char *) buf; sprintf (buf, ".+%ld", (long) value); errmsg = cgen_parse_address (cd, &bufp, opindex, code, &result_type, &value); } if (result_type == CGEN_PARSE_OPERAND_RESULT_QUEUED) { /* This will happen for things like (s2-s1) where s2 and s1 are labels. */ /* Nothing further to be done. */ } else errmsg = _("Not a pc-relative address."); } return errmsg; } /* -- dis.c */ #define CGEN_PRINT_INSN epiphany_print_insn static int epiphany_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { bfd_byte buf[CGEN_MAX_INSN_SIZE]; int buflen; int status; info->bytes_per_chunk = 2; /* Attempt to read the base part of the insn. */ info->bytes_per_line = buflen = cd->base_insn_bitsize / 8; status = (*info->read_memory_func) (pc, buf, buflen, info); /* Try again with the minimum part, if min < base. */ if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) { info->bytes_per_line = buflen = cd->min_insn_bitsize / 8; status = (*info->read_memory_func) (pc, buf, buflen, info); } if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } return print_insn (cd, pc, info, buf, buflen); } static void print_postindex (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, value ? "-" : "+"); } static void print_simm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { print_address (cd, dis_info, value, attrs, pc, length); } static void print_uimm_not_reg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void * dis_info, unsigned long value, unsigned int attrs ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *)dis_info; if (value & 0x800) (*info->fprintf_func) (info->stream, "-"); value &= 0x7ff; print_address (cd, dis_info, value, attrs, pc, length); } /* -- */ @