head 1.17; access; symbols perseant-exfatfs-base-20261102:1.17 netbsd-11-1-RELEASE:1.15 netbsd-10-2-RELEASE:1.14 netbsd-9-5-RELEASE:1.7.2.3 netbsd-11-0-RELEASE:1.15 netbsd-11-0-RC7:1.15 netbsd-11-0-RC6:1.15 netbsd-11-0-RC5:1.15 netbsd-11-0-RC4:1.15 netbsd-11-0-RC3:1.15 netbsd-11-0-RC2:1.15 netbsd-11-0-RC1:1.15 perseant-exfatfs-base-20250801:1.15 netbsd-11:1.15.0.8 netbsd-11-base:1.15 netbsd-10-1-RELEASE:1.14 perseant-exfatfs-base-20240630:1.15 perseant-exfatfs:1.15.0.6 perseant-exfatfs-base:1.15 netbsd-9-4-RELEASE:1.7.2.3 netbsd-10-0-RELEASE:1.14 netbsd-10-0-RC6:1.14 netbsd-10-0-RC5:1.14 netbsd-10-0-RC4:1.14 netbsd-10-0-RC3:1.14 netbsd-10-0-RC2:1.14 thorpej-ifq:1.15.0.4 thorpej-ifq-base:1.15 thorpej-altq-separation:1.15.0.2 thorpej-altq-separation-base:1.15 netbsd-10-0-RC1:1.14 netbsd-10:1.14.0.4 netbsd-10-base:1.14 bouyer-sunxi-drm:1.14.0.2 bouyer-sunxi-drm-base:1.14 netbsd-9-3-RELEASE:1.7.2.3 thorpej-i2c-spi-conf2:1.11.0.16 thorpej-i2c-spi-conf2-base:1.11 thorpej-futex2:1.11.0.14 thorpej-futex2-base:1.11 thorpej-cfargs2:1.11.0.12 thorpej-cfargs2-base:1.11 cjep_sun2x-base1:1.11 cjep_sun2x:1.11.0.10 cjep_sun2x-base:1.11 cjep_staticlib_x-base1:1.11 netbsd-9-2-RELEASE:1.7.2.3 cjep_staticlib_x:1.11.0.8 cjep_staticlib_x-base:1.11 thorpej-i2c-spi-conf:1.11.0.6 thorpej-i2c-spi-conf-base:1.11 thorpej-cfargs:1.11.0.4 thorpej-cfargs-base:1.11 thorpej-futex:1.11.0.2 thorpej-futex-base:1.11 netbsd-9-1-RELEASE:1.7.2.3 bouyer-xenpvh-base2:1.10 phil-wifi-20200421:1.10 bouyer-xenpvh-base1:1.10 phil-wifi-20200411:1.10 bouyer-xenpvh:1.10.0.6 bouyer-xenpvh-base:1.10 is-mlppp:1.10.0.4 is-mlppp-base:1.10 phil-wifi-20200406:1.10 ad-namecache-base3:1.10 netbsd-9-0-RELEASE:1.7.2.2 netbsd-9-0-RC2:1.7.2.2 ad-namecache-base2:1.10 ad-namecache-base1:1.10 ad-namecache:1.10.0.2 ad-namecache-base:1.10 netbsd-9-0-RC1:1.7.2.1 phil-wifi-20191119:1.9 netbsd-9:1.7.0.2 netbsd-9-base:1.7 phil-wifi:1.5.0.2 phil-wifi-20190609:1.5 isaki-audio2:1.3.0.2 isaki-audio2-base:1.3 pgoyette-compat-merge-20190127:1.1.2.2 pgoyette-compat-20190127:1.1 pgoyette-compat-20190118:1.1 pgoyette-compat-1226:1.1 pgoyette-compat-1126:1.1 pgoyette-compat-1020:1.1 pgoyette-compat-0930:1.1 pgoyette-compat:1.1.0.2 pgoyette-compat-0906:1.1; locks; strict; comment @# @; 1.17 date 2026.01.18.08.31.42; author skrll; state dead; branches; next 1.16; commitid 5OqALNTX2VwOOQqG; 1.16 date 2026.01.18.05.50.28; author skrll; state Exp; branches; next 1.15; commitid vOpgNH0EDoi6VPqG; 1.15 date 2023.08.30.21.26.05; author rjs; state Exp; branches 1.15.6.1; next 1.14; commitid FthmZOOHLL898RCE; 1.14 date 2021.11.07.17.11.43; author jmcneill; state Exp; branches; next 1.13; commitid Py6px4DzHropYSfD; 1.13 date 2021.10.02.20.41.47; author mrg; state Exp; branches; next 1.12; commitid 15bOIIdjvwOSghbD; 1.12 date 2021.09.03.01.21.48; author mrg; state Exp; branches; next 1.11; commitid z3fTiJMCVFzINr7D; 1.11 date 2020.05.17.19.57.25; author riastradh; state Exp; branches; next 1.10; commitid pyytm70SnAbgdD8C; 1.10 date 2019.12.19.00.52.29; author jakllsch; state Exp; branches; next 1.9; commitid cDrBRhngUdanHfPB; 1.9 date 2019.11.16.13.24.25; author jmcneill; state Exp; branches; next 1.8; commitid KjKodCQN4EQiV4LB; 1.8 date 2019.08.13.17.24.25; author tnn; state Exp; branches; next 1.7; commitid Z9v26tHtZ0oOiTyB; 1.7 date 2019.07.28.10.03.56; author jmcneill; state Exp; branches 1.7.2.1; next 1.6; commitid cghFj45WcXOJnNwB; 1.6 date 2019.06.12.10.13.44; author jmcneill; state Exp; branches; next 1.5; commitid HVEEAfugzGQJUSqB; 1.5 date 2019.05.01.10.43.55; author jmcneill; state Exp; branches 1.5.2.1; next 1.4; commitid DNkS0Lawxt5xqulB; 1.4 date 2019.04.30.23.42.53; author jmcneill; state dead; branches; next 1.3; commitid YvSxSak7U8dXLqlB; 1.3 date 2019.04.10.23.30.28; author jakllsch; state Exp; branches; next 1.2; commitid VmcAlIjEfhx1lRiB; 1.2 date 2019.03.07.00.35.22; author jakllsch; state Exp; branches; next 1.1; commitid hCBZ66Y5VBN7NmeB; 1.1 date 2018.08.12.18.01.03; author jmcneill; state Exp; branches 1.1.2.1; next ; commitid 7HuoHEpofruVgRNA; 1.15.6.1 date 2026.11.04.23.20.08; author perseant; state dead; branches; next ; commitid 3QTNojfCEH9lUb2H; 1.7.2.1 date 2019.11.16.16.48.26; author martin; state Exp; branches; next 1.7.2.2; commitid Y2IhGDRNnw3h36LB; 1.7.2.2 date 2020.01.21.10.39.59; author martin; state Exp; branches; next 1.7.2.3; commitid OMO1MJHdXErlTxTB; 1.7.2.3 date 2020.05.18.18.54.30; author martin; state Exp; branches; next ; commitid lR3WPBt8ULqQPK8C; 1.5.2.1 date 2019.05.01.10.43.55; author christos; state dead; branches; next 1.5.2.2; commitid jtc8rnCzWiEEHGqB; 1.5.2.2 date 2019.06.10.22.05.53; author christos; state Exp; branches; next 1.5.2.3; commitid jtc8rnCzWiEEHGqB; 1.5.2.3 date 2020.04.13.08.03.33; author martin; state Exp; branches; next ; commitid X01YhRUPVUDaec4C; 1.1.2.1 date 2018.08.12.18.01.03; author pgoyette; state dead; branches; next 1.1.2.2; commitid HCi1bXD317XIK0RA; 1.1.2.2 date 2018.09.06.06.55.26; author pgoyette; state Exp; branches; next ; commitid HCi1bXD317XIK0RA; desc @@ 1.17 log @Remove files that are no longer needed. @ text @@ 1.16 log @Update to handle the new DTS import. - Arm re-organisation - new dtb/dtbo files - removal of local additions where upstream has caught up @ text @@ 1.15 log @Re-enable the fan. @ text @a0 149 /* $NetBSD: rk3399-rockpro64.dts,v 1.14 2021/11/07 17:11:43 jmcneill Exp $ */ /*- * Copyright (c) 2019,2021 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "../../../external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts" #include "rk3399-crypto.dtsi" / { backlight: lcd-backlight { compatible = "pwm-backlight"; pwms = <&pwm0 0 25000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; default-brightness-level = <200>; status = "disabled"; }; edp_panel: edp-panel { compatible = "simple-panel"; backlight = <&backlight>; power-supply = <&vcc3v3_s0>; pinctrl-names = "default"; pinctrl-0 = <&edp_panel_en>; enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; prepare-delay-ms = <20>; enable-delay-ms = <20>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; panel_in_edp: endpoint@@0 { reg = <0>; remote-endpoint = <&edp_out_panel>; }; }; }; }; edp@@ff970000 { ports { edp_out: port@@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; edp_out_panel: endpoint@@0 { reg = <0>; remote-endpoint = <&panel_in_edp>; }; }; }; }; fan: pwm-fan { cooling-levels = <0 100 150 200 255>; }; #if 0 edp@@ff970000 { status = "okay"; }; edp-panel { status = "okay"; }; pwm@@ff420000 { status = "okay"; }; lcd-backlight { status = "okay"; }; #endif }; &pinctrl { lcd_panel { edp_panel_en: edp-panel-en { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; &pcie0 { bus-scan-delay-ms = <1000>; }; @ 1.15.6.1 log @Sync with HEAD @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.15 2023/08/30 21:26:05 rjs Exp $ */ @ 1.14 log @arm: dts: adapt for dts-5.15 @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.13 2021/10/02 20:41:47 mrg Exp $ */ d116 4 @ 1.13 log @default RK3399 PCIe to 1.x. sometime in mid-2019, rockchip disabled PCIe 2.x referrencing a non-public errata in linux and the dts, both of which were changed to default to only PCIe 1.x (in code, and in DT.) see: https://lore.kernel.org/all/1481881357-1793-1-git-send-email-shawn.lin@@rock-chips.com/ we haven't observed any specific problems, but we've also tested far fewer cards than linux. there are other issues such as what happens for a PCI abort depending on which CPU triggers it we do not currently handle either. tested on rockpro64 with nvme & ahcisata, and pinebook pro nvme. still allows DT to set back to '2' if the user so desires. @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.12 2021/09/03 01:21:48 mrg Exp $ */ d4 1 a4 1 * Copyright (c) 2019 Jared McNeill a32 18 pwm-fan { compatible = "pwm-fan"; status = "okay"; pwms = <&pwm1 0 40000 0>; cooling-levels = <0 150 195 240>; }; vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_pwr_en>; regulator-name = "vcc3v3_pcie"; }; a140 20 pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; pcie_clkreqn: pci-clkreqn { rockchip,pins = <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; }; }; }; &pwm1 { status = "okay"; }; &pcie_phy { status = "okay"; a143 5 ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn>; vpcie3v3-supply = <&vcc3v3_pcie>; a144 14 status = "okay"; }; &spi1 { status = "okay"; spiflash { compatible = "jedec,spi-nor"; reg = <0>; status = "okay"; }; }; &hdmi_sound { status = "okay"; @ 1.12 log @rk3399 pcie: pay attention to the "bus-scan-delay-ms" property. our existing pinebookpro DTS, but not the other rk3399 ones, have this property set to "1000" (it's the same in linux 5.14 DTS.) as there are already static 100ms + upto 1000ms, count how many are done, and only delay more to complete one second. this allows reverting this device-specific change: http://mail-index.netbsd.org/source-changes/2021/06/23/msg130402.html and makes other sorts of storage cards more likely to work as well. tested on rockpro64. XXX: consider moving dts setting into rk3399.dtsi. ok jmcneill jak inspired by https://gitlab.manjaro.org/manjaro-arm/packages/core/linux/-/blob/master/0013-rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.11 2020/05/17 19:57:25 riastradh Exp $ */ a183 1 max-link-speed = <2>; @ 1.11 log @Rockchip crypto engine RNG driver. As found on the rk3288 and rk3399. This driver only supports the TRNG, not the rest of the crypto engine, although it uses the AES unit to do a self-test at attach time to verify that the engine works. There seem to be two versions of the Rockchip crypto engine, v1 and v2; this one is for v1. Can't name a driver `rkcryptov1' so we'll clumsily call it `rkv1crypto' instead to leave room for `rkv2crypto' later on. The crypto binding derived from the Rockchip BSP Linux kernel, in the location it appears on the rk3399, is in rk3399-crypto.dtsi, since there doesn't seem to be a better place to put it at the moment among this twisty maze of inclusions, all different. @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.10 2019/12/19 00:52:29 jakllsch Exp $ */ d188 1 @ 1.10 log @add template bits for optional eDP panel on RockPro64 @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.9 2019/11/16 13:24:25 jmcneill Exp $ */ d30 1 a150 1 @ 1.9 log @Enable HDMI audio on ROCKPro64 @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.8 2019/08/13 17:24:25 tnn Exp $ */ d49 102 d154 6 @ 1.8 log @rk3399-rockpro64.dts: enable spi1 and add spiflash as a child node @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.7 2019/07/28 10:03:56 jmcneill Exp $ */ d91 4 @ 1.7 log @Set max link speed, remove assigned clocks @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.6 2019/06/12 10:13:44 jmcneill Exp $ */ d82 9 @ 1.7.2.1 log @Pull up following revision(s) (requested by jmcneill in ticket #427): sys/dev/ic/dw_hdmi_phy.c: revision 1.2 sys/dev/ic/dw_hdmi.c: revision 1.4 sys/dev/fdt/ausoc.c: revision 1.5 sys/dev/ic/dw_hdmi.h: revision 1.2 sys/dev/ic/dw_hdmi.h: revision 1.3 sys/dev/ic/dw_hdmi.h: revision 1.4 sys/conf/files: revision 1.1242 sys/dev/fdt/fdtvar.h: revision 1.57 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.11 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.12 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.13 sys/arch/evbarm/conf/GENERIC64: revision 1.110 sys/arch/arm/rockchip/rk_drm.c: revision 1.1 sys/arch/arm/rockchip/rk_drm.c: revision 1.2 sys/arch/evbarm/conf/GENERIC64: revision 1.112 sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.1 sys/dev/fdt/fdt_clock.c: revision 1.10 sys/arch/evbarm/conf/GENERIC64: revision 1.113 sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.2 sys/arch/arm/rockchip/rk_drm.h: revision 1.1 sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.3 sys/arch/arm/rockchip/rk_fb.c: revision 1.1 sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.9 sys/arch/arm/rockchip/rk_vop.c: revision 1.1 sys/arch/arm/rockchip/rk_vop.c: revision 1.2 sys/arch/arm/rockchip/rk_i2c.c: revision 1.6 sys/arch/arm/rockchip/rk_cru.h: revision 1.6 sys/arch/arm/rockchip/rk_cru.h: revision 1.7 sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.4 sys/arch/arm/rockchip/rk_cru_composite.c: revision 1.5 sys/arch/arm/rockchip/files.rockchip: revision 1.21 sys/arch/arm/rockchip/rk_i2s.c: revision 1.1 sys/arch/arm/rockchip/files.rockchip: revision 1.22 sys/dev/ic/dw_hdmi.c: revision 1.2 sys/dev/ic/dw_hdmi_phy.c: revision 1.1 sys/dev/ic/dw_hdmi.c: revision 1.3 Support reads of more than 32 bytes in a single xfer. Add support for internal DesignWare HDMI PHYs Add fdtbus_clock_enable and fdtbus_clock_enable_index shortcuts Add HDMI and VOP clocks WIP display driver for Rockchip RK3399 Add (commented out) Rockchip display support Select the correct MPLL and PHY settings for the requested pixel clock Force DCLK_VOP0/1 dividers to 1 and select closest match when setting PLL rates. Fix typo in phy config table Fix a few swapped fields Remove debug output Enable Rockchip display support Set sysclk rate at set_format time, so the link set_format callback can read the new sysclk Add I2S audio input support. Add software volume controls. Add support for I2S clocks. Add driver for Rockchip I2S/PCM controller. Enable HDMI audio on ROCKPro64 Add rki2s Add audio support @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.7 2019/07/28 10:03:56 jmcneill Exp $ */ a64 4 &hdmi_sound { status = "okay"; }; @ 1.7.2.2 log @Pull up following revision(s) (requested by mrg in ticket #616): sys/dev/ic/anx_dp.c: revision 1.2 sys/arch/evbarm/conf/GENERIC64: revision 1.126 sys/dev/ic/anx_dp.h: revision 1.1 sys/arch/evbarm/conf/GENERIC64: revision 1.128 sys/dev/ic/anx_dp.h: revision 1.2 sys/dev/fdt/dwcmmc_fdt.c: revision 1.9 sys/dev/i2c/cwfg.c: revision 1.1 sys/conf/files: revision 1.1247 sys/dev/fdt/pwm_backlight.c: revision 1.5 sys/dev/fdt/pwm_backlight.c: revision 1.6 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.14 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.15 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.16 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.17 sys/dev/ic/dwc_mmc.c: revision 1.20 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.18 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.19 sys/dev/usb/usbdevs: revision 1.775 sys/arch/arm/rockchip/rk_dwhdmi.c: revision 1.4 sys/dev/fdt/simple_amplifier.c: revision 1.1 sys/dev/i2c/files.i2c: revision 1.105 sys/arch/evbarm/conf/GENERIC64: revision 1.117 sys/arch/evbarm/conf/GENERIC64: revision 1.118 sys/dev/i2c/files.i2c: revision 1.107 sys/dev/fdt/files.fdt: revision 1.49 sys/arch/arm/rockchip/rk_anxdp.c: revision 1.1 sys/dev/ic/dwc_mmc_var.h: revision 1.9 sys/dev/i2c/rkpmic.c: revision 1.4 sys/arch/arm/rockchip/rk_anxdp.c: revision 1.2 sys/dev/i2c/rkpmic.c: revision 1.5 sys/dev/i2c/rkpmic.c: revision 1.6 sys/arch/arm/rockchip/rk_vop.c: revision 1.4 sys/arch/arm/rockchip/rk_vop.c: revision 1.5 sys/dev/i2c/rkpmic.c: revision 1.8 sys/arch/arm/dts/rk3399-pinebook-pro.dts: revision 1.1 sys/dev/usb/ums.c: revision 1.96 (via patch) sys/arch/arm/rockchip/rk_pwm.c: revision 1.3 sys/arch/arm/dts/rk3399-pinebook-pro.dts: revision 1.2 sys/dev/i2c/es8316ac.c: revision 1.1 sys/dev/fdt/dwcmmc_fdt.c: revision 1.10 sys/dev/i2c/es8316ac.c: revision 1.2 sys/dev/fdt/fdt_panel.c: revision 1.1 sys/dev/ic/dwc_mmc.c: revision 1.18 sys/dev/fdt/fdt_panel.c: revision 1.2 sys/dev/ic/dwc_mmc.c: revision 1.19 sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.10 sys/dev/fdt/fdt_port.c: revision 1.5 sys/dev/ic/dwc_mmc_var.h: revision 1.10 sys/dev/fdt/fdt_port.c: revision 1.6 sys/arch/evbarm/conf/GENERIC64: revision 1.122 sys/dev/ic/dwc_mmc_var.h: revision 1.11 sys/dev/fdt/files.fdt: revision 1.50 sys/arch/evbarm/conf/GENERIC64: revision 1.123 sys/arch/arm/rockchip/rk_i2s.c: revision 1.2 sys/arch/arm/rockchip/files.rockchip: revision 1.23 sys/arch/evbarm/conf/GENERIC64: revision 1.124 sys/dev/ic/anx_dp.c: revision 1.1 rkpmic: add RTC support; register w/ todr(9) rkpmic: correct delay Add support for SDIO interrupts. fix copy/paste error in mux_pll_src_cpll_gpll_ppll_parents[] add RK3399 eDP clocks add RK3399 DisplayPort clocks style fix/KNF rk3399_cru: implement dclk_vop0_frac and dclk_vop1_frac Move drm_encoder from rkvop(4) to the SoC-layer output pipe drivers (rk_dwhdmi). rkvop: set stride using virtual framebuffer width instead of display mode rk3399_cru: Reparent dclk_vop[01] to gpll via dclk_vop[01]_frac. The previous source of dclk_vop[01] was vpll via dclk_vop[01]_div. vpll is apparently used directly as a pixel clock source for the HDMI PHY, and we don't want the other VOP's dclk changing out from under it because we can't handle finding a replacement clock source with the right rate yet. gpll happens to run at 594MHz, which works well as a basis for pixel clocks. Linux suggests that the source clock of the fractional divider needs to be more than twenty times greater than the resulting clock (or some intermediate clock?) for output stability. This may not be the case with 594MHz and the common pixel clocks I see used by displays in my area of the wild, but it works for now. add Analogix DisplayPort core driver add Rockchip (RK3399) glue for Analogix DisplayPort core add anxdp(4) Add another panel@@fdt driver, this time for DRM-style panels. To do: migrate away from other panel driver. enable panel at fdt drivers paper over the rkpwm get_conf function that otherwise doesn't seem to let things work add template bits for optional eDP panel on RockPro64 Abort panel driver attach if required regulator is missing. Add clk provider Add Pinebook Pro dts, from Manjaro Linux. https://gitlab.manjaro.org/tsys/linux-pinebook-pro/blob/877ca0e7283596f37845de50dc36bff5b88b91e1/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts + rk3399-pinebook-pro.dts Attach mmcpwrseq resource earlier dwcmmc improvements: - Use mmcpwrseq resources if available - Only set 4- or 8-bit mode if specified in the dt properties - Add quirk for implementations with inverted power enable logic - Support switching signal voltage between 1.8V and 3.3V - Fix a clock divider issue on Rockchip SoCs Fix performance regression with previous Quiet chatty printfs No need to print all supported levels at attach, print the range and total number of steps Disable SPI for now (rkspi driver hangs at boot) Add driver for simple-audio-amplifier binding Add driver for Everest Semi ES8316 Low Power Audio CODEC add es8316, simpleamp Avoid sleeping while the audio intr lock is held. If the rockchip,system-power-controller property is present, try to power off with the PMIC Add HAILUCK keyboard (product 1e) Add a quirk for the HAILUCK USB keyboard / touchpad device with product 1e. The keyboard does not function properly unless the touchpad's intr endpoint is active. Add driver for CellWise CW2015 Fuel Gauge IC. add cwfg Emit PMFE_DISPLAY_{ON,OFF} events in response to DPMS requests. If the backlight node does not have an enable gpio, set the lowest duty cycle to turn the display off instead. Attach psci as early as possible. This allows other power controllers to register their own poweroff / reset callbacks with a higher preference. Add 2000 MHz to available armclkb rates Remove debug printfs @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.7.2.1 2019/11/16 16:48:26 martin Exp $ */ a48 102 backlight: lcd-backlight { compatible = "pwm-backlight"; pwms = <&pwm0 0 25000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; default-brightness-level = <200>; status = "disabled"; }; edp_panel: edp-panel { compatible = "simple-panel"; backlight = <&backlight>; power-supply = <&vcc3v3_s0>; pinctrl-names = "default"; pinctrl-0 = <&edp_panel_en>; enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; prepare-delay-ms = <20>; enable-delay-ms = <20>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; panel_in_edp: endpoint@@0 { reg = <0>; remote-endpoint = <&edp_out_panel>; }; }; }; }; edp@@ff970000 { ports { edp_out: port@@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; edp_out_panel: endpoint@@0 { reg = <0>; remote-endpoint = <&panel_in_edp>; }; }; }; }; #if 0 edp@@ff970000 { status = "okay"; }; edp-panel { status = "okay"; }; pwm@@ff420000 { status = "okay"; }; lcd-backlight { status = "okay"; }; #endif a51 6 lcd_panel { edp_panel_en: edp-panel-en { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; @ 1.7.2.3 log @Pull up following revision(s) (requested by riastradh in ticket #913): sys/arch/arm/dts/rk3399-crypto.dtsi: revision 1.1 sys/arch/arm/rockchip/rk_v1crypto.c: revision 1.1 sys/arch/arm/rockchip/rk_v1crypto.c: revision 1.2 (plus patch) sys/arch/arm/rockchip/rk_v1crypto.h: revision 1.1 sys/arch/arm/dts/rk3399-pinebook-pro.dts: revision 1.3 sys/arch/arm/rockchip/rk3399_cru.c: revision 1.20 sys/arch/evbarm/conf/GENERIC64: revision 1.158 sys/arch/arm/dts/rk3399-rockpro64.dts: revision 1.11 sys/arch/arm/rockchip/files.rockchip: revision 1.24 Rockchip crypto engine RNG driver. As found on the rk3288 and rk3399. This driver only supports the TRNG, not the rest of the crypto engine, although it uses the AES unit to do a self-test at attach time to verify that the engine works. There seem to be two versions of the Rockchip crypto engine, v1 and v2; this one is for v1. Can't name a driver `rkcryptov1' so we'll clumsily call it `rkv1crypto' instead to leave room for `rkv2crypto' later on. The crypto binding derived from the Rockchip BSP Linux kernel, in the location it appears on the rk3399, is in rk3399-crypto.dtsi, since there doesn't seem to be a better place to put it at the moment among this twisty maze of inclusions, all different. Use rnd_add_data_sync from the callback. (Doesn't make a difference in HEAD but this is the stated API contract and it matters if we want to pull this up.) Prime the pool on attach. @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.7.2.2 2020/01/21 10:39:59 martin Exp $ */ a29 1 #include "rk3399-crypto.dtsi" d150 1 @ 1.6 log @Enable RK3399 PCIe. @ text @d1 1 a1 1 /* $NetBSD: rk3399-rockpro64.dts,v 1.5 2019/05/01 10:43:55 jmcneill Exp $ */ a73 4 assigned-clocks = <&cru SCLK_PCIEPHY_REF>; assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; assigned-clock-rates = <100000000>; d76 1 @ 1.5 log @Enable pwm1 and add a pwm-fan node to enable the +FAN- header on ROCKPro64 @ text @d1 1 a1 1 /* $NetBSD$ */ d38 25 d68 17 @ 1.5.2.1 log @file rk3399-rockpro64.dts was added on branch phil-wifi on 2019-06-10 22:05:53 +0000 @ text @d1 42 @ 1.5.2.2 log @Sync with HEAD @ text @a0 42 /* $NetBSD: rk3399-rockpro64.dts,v 1.5 2019/05/01 10:43:55 jmcneill Exp $ */ /*- * Copyright (c) 2019 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "../../../external/gpl2/dts/dist/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dts" / { pwm-fan { compatible = "pwm-fan"; status = "okay"; pwms = <&pwm1 0 40000 0>; cooling-levels = <0 150 195 240>; }; }; &pwm1 { status = "okay"; }; @ 1.5.2.3 log @Mostly merge changes from HEAD upto 20200411 @ text @d1 1 a1 1 /* $NetBSD$ */ a37 133 vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_pwr_en>; regulator-name = "vcc3v3_pcie"; }; backlight: lcd-backlight { compatible = "pwm-backlight"; pwms = <&pwm0 0 25000 0>; brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; default-brightness-level = <200>; status = "disabled"; }; edp_panel: edp-panel { compatible = "simple-panel"; backlight = <&backlight>; power-supply = <&vcc3v3_s0>; pinctrl-names = "default"; pinctrl-0 = <&edp_panel_en>; enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; prepare-delay-ms = <20>; enable-delay-ms = <20>; status = "disabled"; ports { #address-cells = <1>; #size-cells = <0>; port@@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; panel_in_edp: endpoint@@0 { reg = <0>; remote-endpoint = <&edp_out_panel>; }; }; }; }; edp@@ff970000 { ports { edp_out: port@@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; edp_out_panel: endpoint@@0 { reg = <0>; remote-endpoint = <&panel_in_edp>; }; }; }; }; #if 0 edp@@ff970000 { status = "okay"; }; edp-panel { status = "okay"; }; pwm@@ff420000 { status = "okay"; }; lcd-backlight { status = "okay"; }; #endif }; &pinctrl { lcd_panel { edp_panel_en: edp-panel-en { rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; pcie_clkreqn: pci-clkreqn { rockchip,pins = <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; }; }; a42 27 &pcie_phy { status = "okay"; }; &pcie0 { ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; max-link-speed = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; }; &spi1 { status = "okay"; spiflash { compatible = "jedec,spi-nor"; reg = <0>; status = "okay"; }; }; &hdmi_sound { status = "okay"; }; @ 1.4 log @Use mainline dts for rockpro64 now. @ text @d1 26 a26 40 /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. d29 1 a29 5 /dts-v1/; #include #include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" d32 1 a32 184 model = "Pine64 RockPro64"; compatible = "pine64,rockpro64", "rockchip,rk3399"; chosen { bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1"; stdout-path = "serial2:1500000n8"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; drm_logo: drm-logo@@00000000 { compatible = "rockchip,drm-logo"; reg = <0x0 0x0 0x0 0x0>; }; }; /* first 64k(0xff8c0000~0xff8d0000) for ddr and suspend */ iram: sram@@ff8d0000 { compatible = "mmio-sram"; reg = <0x0 0xff8d0000 0x0 0x20000>; /* 128k */ }; aliases { ethernet0 = &gmac; }; dc_12v: dc-12v { compatible = "regulator-fixed"; regulator-name = "dc_12v"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; vcc1v8_s0: vcc1v8-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_s0"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; vin-supply = <&dc_12v>; }; vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_phy"; regulator-always-on; regulator-boot-on; }; vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; vin-supply = <&vcc_sys>; }; vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; regulator-name = "vcc5v0_host"; regulator-always-on; }; vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-always-on; regulator-boot-on; /* for rockchip boot on */ rockchip,pwm_id= <2>; rockchip,pwm_voltage = <900000>; }; clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; clock-output-names = "clkin_gmac"; #clock-cells = <0>; }; spdif_out: spdif-out { status = "okay"; compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>; clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; /* * On the module itself this is one of these (depending * on the actual card populated): * - SDIO_RESET_L_WL_REG_ON * - PDN (power down when low) */ reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; }; xin32k: xin32k { compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "xin32k"; #clock-cells = <0>; }; wireless-wlan { compatible = "wlan-platdata"; rockchip,grf = <&grf>; wifi_chip_type = "ap6354"; sdio_vref = <1800>; WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; wireless-bluetooth { compatible = "bluetooth-platdata"; clocks = <&rk808 1>; clock-names = "ext_clock"; uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "rts_gpio"; pinctrl-0 = <&uart0_rts>; pinctrl-1 = <&uart0_gpios>; BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; BT,wake_gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; status = "okay"; }; hdmi_dp_sound: hdmi-dp-sound { status = "okay"; compatible = "rockchip,rk3399-hdmi-dp"; rockchip,cpu = <&i2s2>; rockchip,codec = <&hdmi>, <&cdn_dp>; }; test-power { status = "okay"; }; leds { status = "okay"; compatible = "gpio-leds"; work-led { gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; mode = <0x23>; }; diy-led { gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; mode = <0x23>; }; }; fan0: pwm-fan { a33 9 pwms = <&pwm1 0 20000000 0>; cooling-min-state = <0>; cooling-max-state = <3>; #cooling-cells = <2>; cooling-levels = <0 102 170 230>; }; rk_key: rockchip-key { compatible = "rockchip,key"; d35 2 a36 319 io-channels = <&saradc 1>; power-key { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; linux,code = <116>; label = "power"; gpio-key,wakeup; }; }; }; &sdmmc { clock-frequency = <50000000>; clock-freq-min-max = <400000 150000000>; supports-sd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; disable-wp; num-slots = <1>; sd-uhs-sdr104; vqmmc-supply = <&vcc_sd>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; card-detect-delay = <800>; status = "okay"; }; &sdio0 { clock-frequency = <50000000>; clock-freq-min-max = <200000 50000000>; supports-sdio; bus-width = <4>; disable-wp; cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; mmc-pwrseq = <&sdio_pwrseq>; non-removable; num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; status = "disabled"; }; &emmc_phy { status = "okay"; }; &sdhci { bus-width = <8>; //mmc-hs400-1_8v; mmc-hs200-1_8v; supports-emmc; non-removable; keep-power-in-suspend; //mmc-hs400-enhanced-strobe; status = "okay"; }; &i2s0 { status = "okay"; rockchip,i2s-broken-burst-len; rockchip,playback-channels = <8>; rockchip,capture-channels = <8>; #sound-dai-cells = <0>; }; &i2s1 { status = "okay"; rockchip,i2s-broken-burst-len; rockchip,playback-channels = <8>; rockchip,capture-channels = <8>; #sound-dai-cells = <0>; }; &i2s2 { status = "okay"; #sound-dai-cells = <0>; }; &spdif { pinctrl-0 = <&spdif_bus_1>; status = "okay"; #sound-dai-cells = <0>; }; &i2c0 { status = "okay"; i2c-scl-rising-time-ns = <180>; i2c-scl-falling-time-ns = <30>; clock-frequency = <400000>; vdd_cpu_b: syr827@@40 { compatible = "silergy,syr827"; reg = <0x40>; regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel1_gpio>; vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; regulator-ramp-delay = <1000>; fcs,suspend-voltage-selector = <1>; regulator-always-on; regulator-boot-on; vin-supply = <&vcc_sys>; regulator-state-mem { regulator-off-in-suspend; }; }; vdd_gpu: syr828@@41 { compatible = "silergy,syr828"; reg = <0x41>; regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel2_gpio>; vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; regulator-ramp-delay = <1000>; fcs,suspend-voltage-selector = <1>; regulator-always-on; regulator-boot-on; vin-supply = <&vcc_sys>; regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ regulator-state-mem { regulator-off-in-suspend; }; }; rk808: pmic@@1b { compatible = "rockchip,rk808"; reg = <0x1b>; interrupt-parent = <&gpio1>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; wakeup-source; #clock-cells = <1>; clock-output-names = "rk808-clkout1", "rk808-clkout2"; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; vcc3-supply = <&vcc_sys>; vcc4-supply = <&vcc_sys>; vcc6-supply = <&vcc_sys>; vcc7-supply = <&vcc_sys>; vcc8-supply = <&vcc3v3_sys>; vcc9-supply = <&vcc_sys>; vcc10-supply = <&vcc_sys>; vcc11-supply = <&vcc_sys>; vcc12-supply = <&vcc3v3_sys>; vddio-supply = <&vcc_1v8>; regulators { vdd_center: DCDC_REG1 { regulator-name = "vdd_center"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vdd_cpu_l: DCDC_REG2 { regulator-name = "vdd_cpu_l"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1350000>; regulator-ramp-delay = <6001>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_ddr: DCDC_REG3 { regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; }; }; vcc_1v8: DCDC_REG4 { regulator-name = "vcc_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; vcc1v8_dvp: LDO_REG1 { regulator-name = "vcc1v8_dvp"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; vcc3v0_touch: LDO_REG2 { regulator-name = "vcc3v0_touch"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; }; }; vcc1v8_pmu: LDO_REG3 { regulator-name = "vcc1v8_pmu"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; vcc_sd: LDO_REG4 { regulator-name = "vcc_sd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3300000>; }; }; vcca3v0_codec: LDO_REG5 { regulator-name = "vcca3v0_codec"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; }; }; vcc_1v5: LDO_REG6 { regulator-name = "vcc_1v5"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1500000>; }; }; vcca1v8_codec: LDO_REG7 { regulator-name = "vcca1v8_codec"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; vcc_3v0: LDO_REG8 { regulator-name = "vcc_3v0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; }; }; vcc3v3_s3: SWITCH_REG1 { regulator-name = "vcc3v3_s3"; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; }; }; vcc3v3_s0: SWITCH_REG2 { regulator-name = "vcc3v3_s0"; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; }; }; }; a39 112 &cpu_l0 { cpu-supply = <&vdd_cpu_l>; }; &cpu_l1 { cpu-supply = <&vdd_cpu_l>; }; &cpu_l2 { cpu-supply = <&vdd_cpu_l>; }; &cpu_l3 { cpu-supply = <&vdd_cpu_l>; }; &cpu_b0 { cpu-supply = <&vdd_cpu_b>; }; &cpu_b1 { cpu-supply = <&vdd_cpu_b>; }; &gpu { status = "okay"; mali-supply = <&vdd_gpu>; }; &tcphy1 { status = "okay"; }; &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; /* tshut polarity 0:LOW 1:HIGH */ rockchip,hw-tshut-polarity = <1>; rockchip,hw-tshut-temp = <110000>; status = "okay"; }; &u2phy0 { status = "okay"; u2phy0_otg: otg-port { status = "okay"; }; u2phy0_host: host-port { phy-supply = <&vcc5v0_host>; status = "okay"; }; }; &u2phy1 { status = "okay"; u2phy1_otg: otg-port { status = "okay"; }; u2phy1_host: host-port { phy-supply = <&vcc5v0_host>; status = "okay"; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts>; status = "disabled"; }; &uart2 { status = "okay"; }; &usb_host0_ehci { status = "okay"; }; &usb_host0_ohci { status = "okay"; }; &usb_host1_ehci { status = "okay"; }; &usb_host1_ohci { status = "okay"; }; &usbdrd3_0 { status = "okay"; }; &usbdrd_dwc3_0 { dr_mode = "otg"; status = "okay"; }; &usbdrd3_1 { status = "okay"; }; &usbdrd_dwc3_1 { dr_mode = "host"; status = "okay"; }; a41 226 pinctrl-names = "active"; }; &pwm3 { status = "okay"; interrupts = ; compatible = "rockchip,remotectl-pwm"; remote_pwm_id = <3>; handle_cpu_id = <1>; remote_support_psci = <1>; ir_key1 { rockchip,usercode = <0x4040>; rockchip,key_table = <0xf2 KEY_REPLY>, <0xba KEY_BACK>, <0xf4 KEY_UP>, <0xf1 KEY_DOWN>, <0xef KEY_LEFT>, <0xee KEY_RIGHT>, <0xbd KEY_HOME>, <0xea KEY_VOLUMEUP>, <0xe3 KEY_VOLUMEDOWN>, <0xe2 KEY_SEARCH>, <0xb2 KEY_POWER>, <0xbc KEY_MUTE>, <0xec KEY_MENU>, <0xbf 0x190>, <0xe0 0x191>, <0xe1 0x192>, <0xe9 183>, <0xe6 248>, <0xe8 185>, <0xe7 186>, <0xf0 388>, <0xbe 0x175>; }; ir_key2 { rockchip,usercode = <0xff00>; rockchip,key_table = <0xf9 KEY_HOME>, <0xbf KEY_BACK>, <0xfb KEY_MENU>, <0xaa KEY_REPLY>, <0xb9 KEY_UP>, <0xe9 KEY_DOWN>, <0xb8 KEY_LEFT>, <0xea KEY_RIGHT>, <0xeb KEY_VOLUMEDOWN>, <0xef KEY_VOLUMEUP>, <0xf7 KEY_MUTE>, <0xe7 KEY_POWER>, <0xfc KEY_POWER>, <0xa9 KEY_VOLUMEDOWN>, <0xa8 KEY_VOLUMEDOWN>, <0xe0 KEY_VOLUMEDOWN>, <0xa5 KEY_VOLUMEDOWN>, <0xab 183>, <0xb7 388>, <0xe8 388>, <0xf8 184>, <0xaf 185>, <0xed KEY_VOLUMEDOWN>, <0xee 186>, <0xb3 KEY_VOLUMEDOWN>, <0xf1 KEY_VOLUMEDOWN>, <0xf2 KEY_VOLUMEDOWN>, <0xf3 KEY_SEARCH>, <0xb4 KEY_VOLUMEDOWN>, <0xbe KEY_SEARCH>; }; ir_key3 { rockchip,usercode = <0x1dcc>; rockchip,key_table = <0xee KEY_REPLY>, <0xf0 KEY_BACK>, <0xf8 KEY_UP>, <0xbb KEY_DOWN>, <0xef KEY_LEFT>, <0xed KEY_RIGHT>, <0xfc KEY_HOME>, <0xf1 KEY_VOLUMEUP>, <0xfd KEY_VOLUMEDOWN>, <0xb7 KEY_SEARCH>, <0xff KEY_POWER>, <0xf3 KEY_MUTE>, <0xbf KEY_MENU>, <0xf9 0x191>, <0xf5 0x192>, <0xb3 388>, <0xbe KEY_1>, <0xba KEY_2>, <0xb2 KEY_3>, <0xbd KEY_4>, <0xf9 KEY_5>, <0xb1 KEY_6>, <0xfc KEY_7>, <0xf8 KEY_8>, <0xb0 KEY_9>, <0xb6 KEY_0>, <0xb5 KEY_BACKSPACE>; }; }; &gmac { phy-supply = <&vcc_phy>; phy-mode = "rgmii"; clock_in_out = "input"; snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; tx_delay = <0x28>; rx_delay = <0x20>; status = "okay"; }; &saradc { status = "okay"; }; &io_domains { status = "okay"; bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ }; &pinctrl { sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; }; }; wireless-bluetooth { uart0_gpios: uart0-gpios { rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb2 { host_vbus_drv: host-vbus-drv { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 21 RK_FUNC_GPIO &pcfg_pull_up>; }; vsel1_gpio: vsel1-gpio { rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_down>; }; vsel2_gpio: vsel2-gpio { rockchip,pins = <1 14 RK_FUNC_GPIO &pcfg_pull_down>; }; }; }; &cluster0_opp { opp-1512000000 { opp-hz = /bits/ 64 <1512000000>; opp-microvolt = <1200000>; clock-latency-ns = <40000>; status = "disabled"; }; }; &cluster1_opp { opp-1992000000 { opp-hz = /bits/ 64 <1992000000>; opp-microvolt = <1300000>; clock-latency-ns = <40000>; status = "disabled"; }; }; &spi1 { status = "okay"; spiflash: spi-flash@@0 { #address-cells = <0x1>; #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <25000000>; status = "okay"; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; loader@@8000 { label = "loader"; reg = <0x0 0x3F8000>; }; env@@3f8000 { label = "env"; reg = <0x3F8000 0x8000>; }; vendor@@7c0000 { label = "vendor"; reg = <0x7C0000 0x40000>; }; }; }; @ 1.3 log @Revert RockPro64 dts changes made for rk3399_pcie. This will need to be re-done differently so as to avoid contention between dts upstream and our driver. @ text @@ 1.2 log @Add RK3399 PCIe host bridge support. Not enabled yet due to occasional hangs during boot, and needing __BUS_SPACE_HAS_PROBING_METHODS enabled. Uses slightly non-standard DT bindings to avoid suboptimality of the Linux binding. This allows for much more flexibility and efficency in allotment of the limited apertures into PCI spaces. @ text @a87 12 vcc3v3_pcie: vcc3v3-pcie-regulator { compatible = "regulator-fixed"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; enable-active-high; gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pcie_pwr_en>; regulator-name = "vcc3v3_pcie"; vin-supply = <&dc_12v>; }; a854 12 pcie { pcie_pwr_en: pcie-pwr-en { rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; }; pcie_clkreqn: pci-clkreqn { rockchip,pins = <2 RK_PD2 RK_FUNC_2 &pcfg_pull_none>; }; }; a874 24 &pcie_phy { status = "okay"; }; &pcie0 { assigned-clocks = <&cru SCLK_PCIEPHY_REF>; assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; assigned-clock-rates = <100000000>; ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; num-lanes = <4>; max-link-speed = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie_clkreqn>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; bus-range = <0 3>; ranges = < 0xc3000000 0x0 0xf8000000 0x0 0xf8000000 0x0 0x2000000 /* 32M region 0, prefmem */ 0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1c00000 /* 28M regions 1-28, mem */ 0x81000000 0x0 0x00000000 0x0 0xfbc00000 0x0 0x0100000 /* 1M region 29, i/o */ 0x00010000 0x0 0x00000000 0x0 0xfbd00000 0x0 0x0300000 /* 3M regions 30-32, config */ >; }; @ 1.1 log @Add dts for ROCKPro64 @ text @d88 12 d867 12 d899 24 @ 1.1.2.1 log @file rk3399-rockpro64.dts was added on branch pgoyette-compat on 2018-09-06 06:55:26 +0000 @ text @d1 907 @ 1.1.2.2 log @Sync with HEAD Resolve a couple of conflicts (result of the uimin/uimax changes) @ text @a0 907 /* * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; #include #include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" / { model = "Pine64 RockPro64"; compatible = "pine64,rockpro64", "rockchip,rk3399"; chosen { bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1"; stdout-path = "serial2:1500000n8"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; drm_logo: drm-logo@@00000000 { compatible = "rockchip,drm-logo"; reg = <0x0 0x0 0x0 0x0>; }; }; /* first 64k(0xff8c0000~0xff8d0000) for ddr and suspend */ iram: sram@@ff8d0000 { compatible = "mmio-sram"; reg = <0x0 0xff8d0000 0x0 0x20000>; /* 128k */ }; aliases { ethernet0 = &gmac; }; dc_12v: dc-12v { compatible = "regulator-fixed"; regulator-name = "dc_12v"; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; vcc1v8_s0: vcc1v8-s0 { compatible = "regulator-fixed"; regulator-name = "vcc1v8_s0"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; }; vcc_sys: vcc-sys { compatible = "regulator-fixed"; regulator-name = "vcc_sys"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-always-on; vin-supply = <&dc_12v>; }; vcc_phy: vcc-phy-regulator { compatible = "regulator-fixed"; regulator-name = "vcc_phy"; regulator-always-on; regulator-boot-on; }; vcc3v3_sys: vcc3v3-sys { compatible = "regulator-fixed"; regulator-name = "vcc3v3_sys"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; vin-supply = <&vcc_sys>; }; vcc5v0_host: vcc5v0-host-regulator { compatible = "regulator-fixed"; enable-active-high; gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&host_vbus_drv>; regulator-name = "vcc5v0_host"; regulator-always-on; }; vdd_log: vdd-log { compatible = "pwm-regulator"; pwms = <&pwm2 0 25000 1>; pwm-supply = <&vcc_sys>; regulator-name = "vdd_log"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-always-on; regulator-boot-on; /* for rockchip boot on */ rockchip,pwm_id= <2>; rockchip,pwm_voltage = <900000>; }; clkin_gmac: external-gmac-clock { compatible = "fixed-clock"; clock-frequency = <125000000>; clock-output-names = "clkin_gmac"; #clock-cells = <0>; }; spdif_out: spdif-out { status = "okay"; compatible = "linux,spdif-dit"; #sound-dai-cells = <0>; }; sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>; clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; /* * On the module itself this is one of these (depending * on the actual card populated): * - SDIO_RESET_L_WL_REG_ON * - PDN (power down when low) */ reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; }; xin32k: xin32k { compatible = "fixed-clock"; clock-frequency = <32768>; clock-output-names = "xin32k"; #clock-cells = <0>; }; wireless-wlan { compatible = "wlan-platdata"; rockchip,grf = <&grf>; wifi_chip_type = "ap6354"; sdio_vref = <1800>; WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; wireless-bluetooth { compatible = "bluetooth-platdata"; clocks = <&rk808 1>; clock-names = "ext_clock"; uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "rts_gpio"; pinctrl-0 = <&uart0_rts>; pinctrl-1 = <&uart0_gpios>; BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; BT,wake_gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; status = "okay"; }; hdmi_dp_sound: hdmi-dp-sound { status = "okay"; compatible = "rockchip,rk3399-hdmi-dp"; rockchip,cpu = <&i2s2>; rockchip,codec = <&hdmi>, <&cdn_dp>; }; test-power { status = "okay"; }; leds { status = "okay"; compatible = "gpio-leds"; work-led { gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "on"; mode = <0x23>; }; diy-led { gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "none"; default-state = "on"; mode = <0x23>; }; }; fan0: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm1 0 20000000 0>; cooling-min-state = <0>; cooling-max-state = <3>; #cooling-cells = <2>; cooling-levels = <0 102 170 230>; }; rk_key: rockchip-key { compatible = "rockchip,key"; status = "okay"; io-channels = <&saradc 1>; power-key { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; linux,code = <116>; label = "power"; gpio-key,wakeup; }; }; }; &sdmmc { clock-frequency = <50000000>; clock-freq-min-max = <400000 150000000>; supports-sd; bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; disable-wp; num-slots = <1>; sd-uhs-sdr104; vqmmc-supply = <&vcc_sd>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; card-detect-delay = <800>; status = "okay"; }; &sdio0 { clock-frequency = <50000000>; clock-freq-min-max = <200000 50000000>; supports-sdio; bus-width = <4>; disable-wp; cap-sd-highspeed; cap-sdio-irq; keep-power-in-suspend; mmc-pwrseq = <&sdio_pwrseq>; non-removable; num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; sd-uhs-sdr104; status = "disabled"; }; &emmc_phy { status = "okay"; }; &sdhci { bus-width = <8>; //mmc-hs400-1_8v; mmc-hs200-1_8v; supports-emmc; non-removable; keep-power-in-suspend; //mmc-hs400-enhanced-strobe; status = "okay"; }; &i2s0 { status = "okay"; rockchip,i2s-broken-burst-len; rockchip,playback-channels = <8>; rockchip,capture-channels = <8>; #sound-dai-cells = <0>; }; &i2s1 { status = "okay"; rockchip,i2s-broken-burst-len; rockchip,playback-channels = <8>; rockchip,capture-channels = <8>; #sound-dai-cells = <0>; }; &i2s2 { status = "okay"; #sound-dai-cells = <0>; }; &spdif { pinctrl-0 = <&spdif_bus_1>; status = "okay"; #sound-dai-cells = <0>; }; &i2c0 { status = "okay"; i2c-scl-rising-time-ns = <180>; i2c-scl-falling-time-ns = <30>; clock-frequency = <400000>; vdd_cpu_b: syr827@@40 { compatible = "silergy,syr827"; reg = <0x40>; regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel1_gpio>; vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; regulator-name = "vdd_cpu_b"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; regulator-ramp-delay = <1000>; fcs,suspend-voltage-selector = <1>; regulator-always-on; regulator-boot-on; vin-supply = <&vcc_sys>; regulator-state-mem { regulator-off-in-suspend; }; }; vdd_gpu: syr828@@41 { compatible = "silergy,syr828"; reg = <0x41>; regulator-compatible = "fan53555-reg"; pinctrl-0 = <&vsel2_gpio>; vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; regulator-name = "vdd_gpu"; regulator-min-microvolt = <712500>; regulator-max-microvolt = <1500000>; regulator-ramp-delay = <1000>; fcs,suspend-voltage-selector = <1>; regulator-always-on; regulator-boot-on; vin-supply = <&vcc_sys>; regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ regulator-state-mem { regulator-off-in-suspend; }; }; rk808: pmic@@1b { compatible = "rockchip,rk808"; reg = <0x1b>; interrupt-parent = <&gpio1>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; rockchip,system-power-controller; wakeup-source; #clock-cells = <1>; clock-output-names = "rk808-clkout1", "rk808-clkout2"; vcc1-supply = <&vcc_sys>; vcc2-supply = <&vcc_sys>; vcc3-supply = <&vcc_sys>; vcc4-supply = <&vcc_sys>; vcc6-supply = <&vcc_sys>; vcc7-supply = <&vcc_sys>; vcc8-supply = <&vcc3v3_sys>; vcc9-supply = <&vcc_sys>; vcc10-supply = <&vcc_sys>; vcc11-supply = <&vcc_sys>; vcc12-supply = <&vcc3v3_sys>; vddio-supply = <&vcc_1v8>; regulators { vdd_center: DCDC_REG1 { regulator-name = "vdd_center"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-ramp-delay = <6001>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vdd_cpu_l: DCDC_REG2 { regulator-name = "vdd_cpu_l"; regulator-min-microvolt = <750000>; regulator-max-microvolt = <1350000>; regulator-ramp-delay = <6001>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-off-in-suspend; }; }; vcc_ddr: DCDC_REG3 { regulator-name = "vcc_ddr"; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; }; }; vcc_1v8: DCDC_REG4 { regulator-name = "vcc_1v8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; vcc1v8_dvp: LDO_REG1 { regulator-name = "vcc1v8_dvp"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; vcc3v0_touch: LDO_REG2 { regulator-name = "vcc3v0_touch"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; }; }; vcc1v8_pmu: LDO_REG3 { regulator-name = "vcc1v8_pmu"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; vcc_sd: LDO_REG4 { regulator-name = "vcc_sd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3300000>; }; }; vcca3v0_codec: LDO_REG5 { regulator-name = "vcca3v0_codec"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; }; }; vcc_1v5: LDO_REG6 { regulator-name = "vcc_1v5"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1500000>; }; }; vcca1v8_codec: LDO_REG7 { regulator-name = "vcca1v8_codec"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <1800000>; }; }; vcc_3v0: LDO_REG8 { regulator-name = "vcc_3v0"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; regulator-suspend-microvolt = <3000000>; }; }; vcc3v3_s3: SWITCH_REG1 { regulator-name = "vcc3v3_s3"; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; }; }; vcc3v3_s0: SWITCH_REG2 { regulator-name = "vcc3v3_s0"; regulator-always-on; regulator-boot-on; regulator-state-mem { regulator-on-in-suspend; }; }; }; }; }; &cpu_l0 { cpu-supply = <&vdd_cpu_l>; }; &cpu_l1 { cpu-supply = <&vdd_cpu_l>; }; &cpu_l2 { cpu-supply = <&vdd_cpu_l>; }; &cpu_l3 { cpu-supply = <&vdd_cpu_l>; }; &cpu_b0 { cpu-supply = <&vdd_cpu_b>; }; &cpu_b1 { cpu-supply = <&vdd_cpu_b>; }; &gpu { status = "okay"; mali-supply = <&vdd_gpu>; }; &tcphy1 { status = "okay"; }; &tsadc { /* tshut mode 0:CRU 1:GPIO */ rockchip,hw-tshut-mode = <1>; /* tshut polarity 0:LOW 1:HIGH */ rockchip,hw-tshut-polarity = <1>; rockchip,hw-tshut-temp = <110000>; status = "okay"; }; &u2phy0 { status = "okay"; u2phy0_otg: otg-port { status = "okay"; }; u2phy0_host: host-port { phy-supply = <&vcc5v0_host>; status = "okay"; }; }; &u2phy1 { status = "okay"; u2phy1_otg: otg-port { status = "okay"; }; u2phy1_host: host-port { phy-supply = <&vcc5v0_host>; status = "okay"; }; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts>; status = "disabled"; }; &uart2 { status = "okay"; }; &usb_host0_ehci { status = "okay"; }; &usb_host0_ohci { status = "okay"; }; &usb_host1_ehci { status = "okay"; }; &usb_host1_ohci { status = "okay"; }; &usbdrd3_0 { status = "okay"; }; &usbdrd_dwc3_0 { dr_mode = "otg"; status = "okay"; }; &usbdrd3_1 { status = "okay"; }; &usbdrd_dwc3_1 { dr_mode = "host"; status = "okay"; }; &pwm1 { status = "okay"; pinctrl-names = "active"; }; &pwm3 { status = "okay"; interrupts = ; compatible = "rockchip,remotectl-pwm"; remote_pwm_id = <3>; handle_cpu_id = <1>; remote_support_psci = <1>; ir_key1 { rockchip,usercode = <0x4040>; rockchip,key_table = <0xf2 KEY_REPLY>, <0xba KEY_BACK>, <0xf4 KEY_UP>, <0xf1 KEY_DOWN>, <0xef KEY_LEFT>, <0xee KEY_RIGHT>, <0xbd KEY_HOME>, <0xea KEY_VOLUMEUP>, <0xe3 KEY_VOLUMEDOWN>, <0xe2 KEY_SEARCH>, <0xb2 KEY_POWER>, <0xbc KEY_MUTE>, <0xec KEY_MENU>, <0xbf 0x190>, <0xe0 0x191>, <0xe1 0x192>, <0xe9 183>, <0xe6 248>, <0xe8 185>, <0xe7 186>, <0xf0 388>, <0xbe 0x175>; }; ir_key2 { rockchip,usercode = <0xff00>; rockchip,key_table = <0xf9 KEY_HOME>, <0xbf KEY_BACK>, <0xfb KEY_MENU>, <0xaa KEY_REPLY>, <0xb9 KEY_UP>, <0xe9 KEY_DOWN>, <0xb8 KEY_LEFT>, <0xea KEY_RIGHT>, <0xeb KEY_VOLUMEDOWN>, <0xef KEY_VOLUMEUP>, <0xf7 KEY_MUTE>, <0xe7 KEY_POWER>, <0xfc KEY_POWER>, <0xa9 KEY_VOLUMEDOWN>, <0xa8 KEY_VOLUMEDOWN>, <0xe0 KEY_VOLUMEDOWN>, <0xa5 KEY_VOLUMEDOWN>, <0xab 183>, <0xb7 388>, <0xe8 388>, <0xf8 184>, <0xaf 185>, <0xed KEY_VOLUMEDOWN>, <0xee 186>, <0xb3 KEY_VOLUMEDOWN>, <0xf1 KEY_VOLUMEDOWN>, <0xf2 KEY_VOLUMEDOWN>, <0xf3 KEY_SEARCH>, <0xb4 KEY_VOLUMEDOWN>, <0xbe KEY_SEARCH>; }; ir_key3 { rockchip,usercode = <0x1dcc>; rockchip,key_table = <0xee KEY_REPLY>, <0xf0 KEY_BACK>, <0xf8 KEY_UP>, <0xbb KEY_DOWN>, <0xef KEY_LEFT>, <0xed KEY_RIGHT>, <0xfc KEY_HOME>, <0xf1 KEY_VOLUMEUP>, <0xfd KEY_VOLUMEDOWN>, <0xb7 KEY_SEARCH>, <0xff KEY_POWER>, <0xf3 KEY_MUTE>, <0xbf KEY_MENU>, <0xf9 0x191>, <0xf5 0x192>, <0xb3 388>, <0xbe KEY_1>, <0xba KEY_2>, <0xb2 KEY_3>, <0xbd KEY_4>, <0xf9 KEY_5>, <0xb1 KEY_6>, <0xfc KEY_7>, <0xf8 KEY_8>, <0xb0 KEY_9>, <0xb6 KEY_0>, <0xb5 KEY_BACKSPACE>; }; }; &gmac { phy-supply = <&vcc_phy>; phy-mode = "rgmii"; clock_in_out = "input"; snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; snps,reset-active-low; snps,reset-delays-us = <0 10000 50000>; assigned-clocks = <&cru SCLK_RMII_SRC>; assigned-clock-parents = <&clkin_gmac>; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; tx_delay = <0x28>; rx_delay = <0x20>; status = "okay"; }; &saradc { status = "okay"; }; &io_domains { status = "okay"; bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ }; &pinctrl { sdio-pwrseq { wifi_enable_h: wifi-enable-h { rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>; }; }; wireless-bluetooth { uart0_gpios: uart0-gpios { rockchip,pins = <2 19 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb2 { host_vbus_drv: host-vbus-drv { rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; pmic { pmic_int_l: pmic-int-l { rockchip,pins = <1 21 RK_FUNC_GPIO &pcfg_pull_up>; }; vsel1_gpio: vsel1-gpio { rockchip,pins = <1 17 RK_FUNC_GPIO &pcfg_pull_down>; }; vsel2_gpio: vsel2-gpio { rockchip,pins = <1 14 RK_FUNC_GPIO &pcfg_pull_down>; }; }; }; &cluster0_opp { opp-1512000000 { opp-hz = /bits/ 64 <1512000000>; opp-microvolt = <1200000>; clock-latency-ns = <40000>; status = "disabled"; }; }; &cluster1_opp { opp-1992000000 { opp-hz = /bits/ 64 <1992000000>; opp-microvolt = <1300000>; clock-latency-ns = <40000>; status = "disabled"; }; }; &spi1 { status = "okay"; spiflash: spi-flash@@0 { #address-cells = <0x1>; #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <25000000>; status = "okay"; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; loader@@8000 { label = "loader"; reg = <0x0 0x3F8000>; }; env@@3f8000 { label = "env"; reg = <0x3F8000 0x8000>; }; vendor@@7c0000 { label = "vendor"; reg = <0x7C0000 0x40000>; }; }; }; }; @