head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC5:1.1.1.3 netbsd-11-0-RC4:1.1.1.3 netbsd-11-0-RC3:1.1.1.3 netbsd-11-0-RC2:1.1.1.3 netbsd-11-0-RC1:1.1.1.3 netbsd-11:1.1.1.3.0.4 netbsd-11-base:1.1.1.3 netbsd-10-1-RELEASE:1.1.1.3 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.3 netbsd-10-0-RC6:1.1.1.3 netbsd-10-0-RC5:1.1.1.3 netbsd-10-0-RC4:1.1.1.3 netbsd-10-0-RC3:1.1.1.3 netbsd-10-0-RC2:1.1.1.3 netbsd-10-0-RC1:1.1.1.3 netbsd-10:1.1.1.3.0.2 netbsd-10-base:1.1.1.3 netbsd-9-3-RELEASE:1.1.1.1 mesa-21-3-7:1.1.1.3 netbsd-9-2-RELEASE:1.1.1.1 netbsd-9-1-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 mesalib-19-1-7:1.1.1.2 netbsd-9:1.1.1.1.0.2 netbsd-9-base:1.1.1.1 mesa-18-3-6:1.1.1.1 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @# @; 1.1 date 2019.03.10.03.42.45; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.45; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2019.09.24.17.23.28; author maya; state Exp; branches; next 1.1.1.3; commitid KJXusGl8fi9AAhEB; 1.1.1.3 date 2022.05.09.01.23.34; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @# Copyright (C) 2016 Intel Corporation. All Rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), # to deal in the Software without restriction, including without limitation # the rights to use, copy, modify, merge, publish, distribute, sublicense, # and/or sell copies of the Software, and to permit persons to whom the # Software is furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice (including the next # paragraph) shall be included in all copies or substantial portions of the # Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING # FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS # IN THE SOFTWARE. # # Provides definitions for events. enum AR_DRAW_TYPE { Instanced = 0, IndexedInstanced = 1, InstancedSplit = 2, IndexedInstancedSplit = 3 }; event ThreadStartApiEvent { }; event ThreadStartWorkerEvent { }; event DrawInfoEvent { uint32_t drawId; AR_DRAW_TYPE type; uint32_t topology; uint32_t numVertices; uint32_t numIndices; int32_t indexOffset; int32_t baseVertex; uint32_t numInstances; uint32_t startInstance; uint32_t tsEnable; uint32_t gsEnable; uint32_t soEnable; uint32_t soTopology; uint32_t splitId; // Split draw count or id. }; event DispatchEvent { uint32_t drawId; uint32_t threadGroupCountX; uint32_t threadGroupCountY; uint32_t threadGroupCountZ; }; event FrameEndEvent { uint32_t frameId; uint32_t nextDrawId; }; ///@@brief API Stat: Synchonization event. event SwrSyncEvent { uint32_t drawId; }; ///@@brief API Stat: Invalidate hot tiles (i.e. tile cache) event SwrInvalidateTilesEvent { uint32_t drawId; }; ///@@brief API Stat: Invalidate and discard hot tiles within pixel region event SwrDiscardRectEvent { uint32_t drawId; }; ///@@brief API Stat: Flush tiles out to memory that is typically owned by driver (e.g. Flush RT cache) event SwrStoreTilesEvent { uint32_t drawId; }; event FrontendStatsEvent { uint32_t drawId; uint64_t IaVertices; uint64_t IaPrimitives; uint64_t VsInvocations; uint64_t HsInvocations; uint64_t DsInvocations; uint64_t GsInvocations; uint64_t GsPrimitives; uint64_t CInvocations; uint64_t CPrimitives; uint64_t SoPrimStorageNeeded0; uint64_t SoPrimStorageNeeded1; uint64_t SoPrimStorageNeeded2; uint64_t SoPrimStorageNeeded3; uint64_t SoNumPrimsWritten0; uint64_t SoNumPrimsWritten1; uint64_t SoNumPrimsWritten2; uint64_t SoNumPrimsWritten3; }; event BackendStatsEvent { uint32_t drawId; uint64_t DepthPassCount; uint64_t PsInvocations; uint64_t CsInvocations; }; event EarlyZSingleSample { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event LateZSingleSample { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event EarlyStencilSingleSample { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event LateStencilSingleSample { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event EarlyZSampleRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event LateZSampleRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event EarlyStencilSampleRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event LateStencilSampleRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; // Total Early-Z counts, SingleSample and SampleRate event EarlyZ { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; // Total LateZ counts, SingleSample and SampleRate event LateZ { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; // Total EarlyStencil counts, SingleSample and SampleRate event EarlyStencil { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; // Total LateStencil counts, SingleSample and SampleRate event LateStencil { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event EarlyZNullPS { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event EarlyStencilNullPS { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event EarlyZPixelRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event LateZPixelRate { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event EarlyOmZ { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event EarlyOmStencil { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event LateOmZ { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event LateOmStencil { uint32_t drawId; uint64_t passCount; uint64_t failCount; }; event GSInputPrims { uint32_t drawId; uint64_t inputPrimCount; }; event GSPrimsGen { uint32_t drawId; uint64_t primGeneratedCount; }; event GSVertsInput { uint32_t drawId; uint64_t vertsInput; }; event TessPrims { uint32_t drawId; uint64_t primCount; }; event RasterTiles { uint32_t drawId; uint32_t rastTileCount; }; event ClipperEvent { uint32_t drawId; uint32_t trivialRejectCount; uint32_t trivialAcceptCount; uint32_t mustClipCount; }; event CullEvent { uint32_t drawId; uint64_t backfacePrimCount; uint64_t degeneratePrimCount; }; event AlphaEvent { uint32_t drawId; uint32_t alphaTestCount; uint32_t alphaBlendCount; }; event VSInfo { uint32_t drawId; uint32_t numInstExecuted; }; event HSInfo { uint32_t drawId; uint32_t numInstExecuted; }; event DSInfo { uint32_t drawId; uint32_t numInstExecuted; }; event GSInfo { uint32_t drawId; uint32_t numInstExecuted; }; event PSInfo { uint32_t drawId; uint32_t numInstExecuted; }; event CSInfo { uint32_t drawId; uint32_t numInstExecuted; };@ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @d99 17 a115 17 uint64_t counter IaVertices; uint64_t counter IaPrimitives; uint64_t counter VsInvocations; uint64_t counter HsInvocations; uint64_t counter DsInvocations; uint64_t counter GsInvocations; uint64_t counter GsPrimitives; uint64_t counter CInvocations; uint64_t counter CPrimitives; uint64_t counter SoPrimStorageNeeded0; uint64_t counter SoPrimStorageNeeded1; uint64_t counter SoPrimStorageNeeded2; uint64_t counter SoPrimStorageNeeded3; uint64_t counter SoNumPrimsWritten0; uint64_t counter SoNumPrimsWritten1; uint64_t counter SoNumPrimsWritten2; uint64_t counter SoNumPrimsWritten3; d121 3 a123 3 uint64_t counter DepthPassCount; uint64_t counter PsInvocations; uint64_t counter CsInvocations; d130 3 a132 3 uint64_t counter passCount; uint64_t counter failCount; }; d137 2 a138 2 uint64_t counter passCount; uint64_t counter failCount; d144 2 a145 2 uint64_t counter passCount; uint64_t counter failCount; d151 2 a152 2 uint64_t counter passCount; uint64_t counter failCount; d158 3 a160 3 uint64_t counter passCount; uint64_t counter failCount; }; d165 2 a166 2 uint64_t counter passCount; uint64_t counter failCount; d172 2 a173 2 uint64_t counter passCount; uint64_t counter failCount; d179 2 a180 2 uint64_t counter passCount; uint64_t counter failCount; d187 3 a189 3 uint64_t counter passCount; uint64_t counter failCount; }; d195 2 a196 2 uint64_t counter passCount; uint64_t counter failCount; d203 2 a204 2 uint64_t counter passCount; uint64_t counter failCount; d211 2 a212 2 uint64_t counter passCount; uint64_t counter failCount; d218 2 a219 2 uint64_t counter passCount; uint64_t counter failCount; d225 2 a226 2 uint64_t counter passCount; uint64_t counter failCount; d232 2 a233 2 uint64_t counter passCount; uint64_t counter failCount; d239 2 a240 2 uint64_t counter passCount; uint64_t counter failCount; d247 2 a248 2 uint64_t counter passCount; uint64_t counter failCount; d254 2 a255 2 uint64_t counter passCount; uint64_t counter failCount; d261 2 a262 2 uint64_t counter passCount; uint64_t counter failCount; d268 2 a269 2 uint64_t counter passCount; uint64_t counter failCount; d275 1 a275 1 uint64_t counter inputPrimCount; d281 1 a281 1 uint64_t counter primGeneratedCount; d287 1 a287 1 uint64_t counter vertsInput; d293 1 a293 1 uint64_t counter primCount; d299 1 a299 1 uint32_t counter rastTileCount; d305 3 a307 3 uint32_t counter trivialRejectCount; uint32_t counter trivialAcceptCount; uint32_t counter mustClipCount; d313 2 a314 2 uint64_t counter backfacePrimCount; uint64_t counter degeneratePrimCount; d320 2 a321 2 uint32_t counter alphaTestCount; uint32_t counter alphaBlendCount; d327 1 a327 12 uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; d333 1 a333 12 uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; d339 1 a339 12 uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; d345 1 a345 13 uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; d351 1 a351 12 uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; d357 1 a357 53 uint32_t counter numInstExecuted; uint32_t counter numSampleExecuted; uint32_t counter numSampleLExecuted; uint32_t counter numSampleBExecuted; uint32_t counter numSampleCExecuted; uint32_t counter numSampleCLZExecuted; uint32_t counter numSampleCDExecuted; uint32_t counter numGather4Executed; uint32_t counter numGather4CExecuted; uint32_t counter numGather4CPOExecuted; uint32_t counter numGather4CPOCExecuted; uint32_t counter numLodExecuted; }; event SWTagFrameEvent { uint64_t swTagFrame; }; event SWTagRenderpassEvent { uint64_t swTagFrame; uint32_t swTagDrawOrDispatch; uint32_t swTagDraw; uint32_t swTagDispatch; uint32_t swTagRenderpassCount; }; event SWTagDrawEvent { uint64_t swTagFrame; uint32_t swTagDrawOrDispatch; uint32_t swTagDraw; uint32_t swTagDispatch; }; event SWTagDispatchEvent { uint64_t swTagFrame; uint32_t swTagDrawOrDispatch; uint32_t swTagDraw; uint32_t swTagDispatch; }; event SWTagFlushEvent { uint64_t swTagFrame; uint32_t swTagDrawOrDispatch; uint32_t swTagDraw; uint32_t swTagDispatch; uint32_t swTagFlushCounter; char swTagFlushReason[256]; uint32_t swTagFlushType; @ 1.1.1.3 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @d32 1 a32 1 event Framework::ThreadStartApiEvent d36 1 a36 1 event Framework::ThreadStartWorkerEvent d40 1 a40 2 ///@@brief Used as a helper event to indicate end of frame. Does not guarantee to capture end of frame on all APIs event ApiSwr::FrameEndEvent d42 14 a55 2 uint32_t frameId; // current frame id uint32_t nextDrawId; // next draw id (always incremental - does not reset) d58 1 a58 2 ///@@brief Synchronization event. event ApiSwr::SwrSyncEvent d61 3 d66 1 a66 2 ///@@brief Invalidate hot tiles (i.e. tile cache) event ApiSwr::SwrInvalidateTilesEvent d68 2 a69 1 uint32_t drawId; d72 2 a73 2 ///@@brief Invalidate and discard hot tiles within pixel region event ApiSwr::SwrDiscardRectEvent d78 2 a79 2 ///@@brief Flush tiles out to memory that is typically owned by driver (e.g. Flush RT cache) event ApiSwr::SwrStoreTilesEvent d84 2 a85 1 event PipelineStats::DrawInfoEvent a87 13 AR_DRAW_TYPE type; // type of draw (indexed, instanced, etc) uint32_t topology; // topology of draw uint32_t numVertices; // number of vertices for draw uint32_t numIndices; // number of indices for draw int32_t indexOffset; // offset into index buffer int32_t baseVertex; // which vertex to start with uint32_t numInstances; // number of instances to draw uint32_t startInstance; // which instance to start fetching uint32_t tsEnable; // tesselation enabled uint32_t gsEnable; // geometry shader enabled uint32_t soEnable; // stream-out enabled uint32_t soTopology; // topology of stream-out uint32_t splitId; // split draw count or id d90 2 a91 1 event PipelineStats::DispatchEvent a93 3 uint32_t threadGroupCountX; // num thread groups in X dimension uint32_t threadGroupCountY; // num thread groups in Y dimension uint32_t threadGroupCountZ; // num thread groups in Z dimension d96 1 a96 1 event PipelineStats::FrontendStatsEvent d99 17 a115 17 uint64_t IaVertices; uint64_t IaPrimitives; uint64_t VsInvocations; uint64_t HsInvocations; uint64_t DsInvocations; uint64_t GsInvocations; uint64_t GsPrimitives; uint64_t CInvocations; uint64_t CPrimitives; uint64_t SoPrimStorageNeeded0; uint64_t SoPrimStorageNeeded1; uint64_t SoPrimStorageNeeded2; uint64_t SoPrimStorageNeeded3; uint64_t SoNumPrimsWritten0; uint64_t SoNumPrimsWritten1; uint64_t SoNumPrimsWritten2; uint64_t SoNumPrimsWritten3; d118 1 a118 1 event PipelineStats::BackendStatsEvent d121 3 a123 3 uint64_t DepthPassCount; uint64_t PsInvocations; uint64_t CsInvocations; d127 1 a127 1 event PipelineStats::EarlyZSingleSample d130 2 a131 2 uint64_t passCount; uint64_t failCount; d134 1 a134 1 event PipelineStats::LateZSingleSample d137 2 a138 2 uint64_t passCount; uint64_t failCount; d141 1 a141 1 event PipelineStats::EarlyStencilSingleSample d144 2 a145 2 uint64_t passCount; uint64_t failCount; d148 1 a148 1 event PipelineStats::LateStencilSingleSample d151 2 a152 2 uint64_t passCount; uint64_t failCount; d155 1 a155 1 event PipelineStats::EarlyZSampleRate d158 2 a159 2 uint64_t passCount; uint64_t failCount; d162 1 a162 1 event PipelineStats::LateZSampleRate d165 2 a166 2 uint64_t passCount; uint64_t failCount; d169 1 a169 1 event PipelineStats::EarlyStencilSampleRate d172 2 a173 2 uint64_t passCount; uint64_t failCount; d176 1 a176 1 event PipelineStats::LateStencilSampleRate d179 2 a180 2 uint64_t passCount; uint64_t failCount; d184 1 a184 1 event PipelineStats::EarlyZ d187 2 a188 2 uint64_t passCount; uint64_t failCount; d192 1 a192 1 event PipelineStats::LateZ d195 2 a196 2 uint64_t passCount; uint64_t failCount; d200 1 a200 1 event PipelineStats::EarlyStencil d203 2 a204 2 uint64_t passCount; uint64_t failCount; d208 1 a208 1 event PipelineStats::LateStencil d211 2 a212 2 uint64_t passCount; uint64_t failCount; d215 1 a215 1 event PipelineStats::EarlyZNullPS d218 2 a219 2 uint64_t passCount; uint64_t failCount; d222 1 a222 1 event PipelineStats::EarlyStencilNullPS d225 2 a226 2 uint64_t passCount; uint64_t failCount; d229 1 a229 1 event PipelineStats::EarlyZPixelRate d232 2 a233 2 uint64_t passCount; uint64_t failCount; d236 1 a236 1 event PipelineStats::LateZPixelRate d239 2 a240 2 uint64_t passCount; uint64_t failCount; d244 1 a244 1 event PipelineStats::EarlyOmZ d247 2 a248 2 uint64_t passCount; uint64_t failCount; d251 1 a251 1 event PipelineStats::EarlyOmStencil d254 2 a255 2 uint64_t passCount; uint64_t failCount; d258 1 a258 1 event PipelineStats::LateOmZ d261 2 a262 2 uint64_t passCount; uint64_t failCount; d265 1 a265 1 event PipelineStats::LateOmStencil d268 2 a269 2 uint64_t passCount; uint64_t failCount; d272 1 a272 1 event PipelineStats::GSInputPrims d275 1 a275 1 uint64_t inputPrimCount; d278 1 a278 1 event PipelineStats::GSPrimsGen d281 1 a281 1 uint64_t primGeneratedCount; d284 1 a284 1 event PipelineStats::GSVertsInput d287 1 a287 1 uint64_t vertsInput; d290 1 a290 1 event PipelineStats::TessPrims d293 1 a293 1 uint64_t primCount; d296 1 a296 1 event PipelineStats::RasterTiles d299 1 a299 1 uint32_t rastTileCount; d302 1 a302 1 event PipelineStats::ClipperEvent d305 3 a307 3 uint32_t trivialRejectCount; uint32_t trivialAcceptCount; uint32_t mustClipCount; d310 1 a310 1 event PipelineStats::CullEvent d313 2 a314 2 uint64_t backfacePrimCount; uint64_t degeneratePrimCount; d317 1 a317 1 event PipelineStats::AlphaEvent d320 2 a321 2 uint32_t alphaTestCount; uint32_t alphaBlendCount; d324 1 a324 1 event ShaderStats::VSInfo d327 12 a338 12 uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; d341 1 a341 1 event ShaderStats::HSInfo d344 12 a355 12 uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; d358 1 a358 1 event ShaderStats::DSInfo d361 12 a372 12 uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; d375 1 a375 1 event ShaderStats::GSInfo d378 12 a389 12 uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; d393 1 a393 1 event ShaderStats::PSInfo d396 12 a407 12 uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; d410 1 a410 1 event ShaderStats::CSInfo d413 26 a438 12 uint32_t numInstExecuted; uint32_t numSampleExecuted; uint32_t numSampleLExecuted; uint32_t numSampleBExecuted; uint32_t numSampleCExecuted; uint32_t numSampleCLZExecuted; uint32_t numSampleCDExecuted; uint32_t numGather4Executed; uint32_t numGather4CExecuted; uint32_t numGather4CPOExecuted; uint32_t numGather4CPOCExecuted; uint32_t numLodExecuted; d441 26 @