head 1.1; branch 1.1.1; access; symbols netbsd-10-2-RELEASE:1.1.1.3 netbsd-9-5-RELEASE:1.1.1.1 netbsd-11-0-RELEASE:1.1.1.3 netbsd-11-0-RC7:1.1.1.3 netbsd-11-0-RC6:1.1.1.3 netbsd-11-0-RC5:1.1.1.3 netbsd-11-0-RC4:1.1.1.3 netbsd-11-0-RC3:1.1.1.3 netbsd-11-0-RC2:1.1.1.3 netbsd-11-0-RC1:1.1.1.3 netbsd-11:1.1.1.3.0.4 netbsd-11-base:1.1.1.3 netbsd-10-1-RELEASE:1.1.1.3 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.3 netbsd-10-0-RC6:1.1.1.3 netbsd-10-0-RC5:1.1.1.3 netbsd-10-0-RC4:1.1.1.3 netbsd-10-0-RC3:1.1.1.3 netbsd-10-0-RC2:1.1.1.3 netbsd-10-0-RC1:1.1.1.3 netbsd-10:1.1.1.3.0.2 netbsd-10-base:1.1.1.3 netbsd-9-3-RELEASE:1.1.1.1 mesa-21-3-7:1.1.1.3 netbsd-9-2-RELEASE:1.1.1.1 netbsd-9-1-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 mesalib-19-1-7:1.1.1.2 netbsd-9:1.1.1.1.0.2 netbsd-9-base:1.1.1.1 mesa-18-3-6:1.1.1.1 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2019.09.24.17.39.44; author maya; state Exp; branches; next 1.1.1.3; commitid KJXusGl8fi9AAhEB; 1.1.1.3 date 2022.05.09.01.23.37; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2014 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ #include "brw_fs.h" #include "brw_fs_live_variables.h" #include "brw_cfg.h" /** @@file brw_fs_dead_code_eliminate.cpp * * Dataflow-aware dead code elimination. * * Walks the instruction list from the bottom, removing instructions that * have results that both aren't used in later blocks and haven't been read * yet in the tail end of this block. */ /** * Is it safe to eliminate the instruction? */ static bool can_eliminate(const fs_inst *inst, BITSET_WORD *flag_live) { return !inst->is_control_flow() && !inst->has_side_effects() && !(flag_live[0] & inst->flags_written()) && !inst->writes_accumulator; } /** * Is it safe to omit the write, making the destination ARF null? */ static bool can_omit_write(const fs_inst *inst) { switch (inst->opcode) { case SHADER_OPCODE_UNTYPED_ATOMIC: case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT: case SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL: case SHADER_OPCODE_TYPED_ATOMIC: case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL: return true; default: /* We can eliminate the destination write for ordinary instructions, * but not most SENDs. */ if (inst->opcode < 128 && inst->mlen == 0) return true; /* It might not be safe for other virtual opcodes. */ return false; } } bool fs_visitor::dead_code_eliminate() { bool progress = false; calculate_live_intervals(); int num_vars = live_intervals->num_vars; BITSET_WORD *live = rzalloc_array(NULL, BITSET_WORD, BITSET_WORDS(num_vars)); BITSET_WORD *flag_live = rzalloc_array(NULL, BITSET_WORD, 1); foreach_block_reverse_safe(block, cfg) { memcpy(live, live_intervals->block_data[block->num].liveout, sizeof(BITSET_WORD) * BITSET_WORDS(num_vars)); memcpy(flag_live, live_intervals->block_data[block->num].flag_liveout, sizeof(BITSET_WORD)); foreach_inst_in_block_reverse_safe(fs_inst, inst, block) { if (inst->dst.file == VGRF) { const unsigned var = live_intervals->var_from_reg(inst->dst); bool result_live = false; for (unsigned i = 0; i < regs_written(inst); i++) result_live |= BITSET_TEST(live, var + i); if (!result_live && (can_omit_write(inst) || can_eliminate(inst, flag_live))) { inst->dst = fs_reg(retype(brw_null_reg(), inst->dst.type)); progress = true; } } if (inst->dst.is_null() && can_eliminate(inst, flag_live)) { inst->opcode = BRW_OPCODE_NOP; progress = true; } if (inst->dst.file == VGRF) { if (!inst->is_partial_write()) { int var = live_intervals->var_from_reg(inst->dst); for (unsigned i = 0; i < regs_written(inst); i++) { BITSET_CLEAR(live, var + i); } } } if (!inst->predicate && inst->exec_size >= 8) flag_live[0] &= ~inst->flags_written(); if (inst->opcode == BRW_OPCODE_NOP) { inst->remove(block); continue; } for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == VGRF) { int var = live_intervals->var_from_reg(inst->src[i]); for (unsigned j = 0; j < regs_read(inst, i); j++) { BITSET_SET(live, var + j); } } } flag_live[0] |= inst->flags_read(devinfo); } } ralloc_free(live); ralloc_free(flag_live); if (progress) invalidate_live_intervals(); return progress; } @ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @d56 1 d58 1 d60 1 @ 1.1.1.3 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @a36 2 using namespace brw; d41 1 a41 2 can_eliminate(const intel_device_info *devinfo, const fs_inst *inst, BITSET_WORD *flag_live) d45 1 a45 1 !(flag_live[0] & inst->flags_written(devinfo)) && d77 3 a79 2 const fs_live_variables &live_vars = live_analysis.require(); int num_vars = live_vars.num_vars; d84 1 a84 1 memcpy(live, live_vars.block_data[block->num].liveout, d86 1 a86 1 memcpy(flag_live, live_vars.block_data[block->num].flag_liveout, d91 1 a91 1 const unsigned var = live_vars.var_from_reg(inst->dst); d98 2 a99 3 (can_omit_write(inst) || can_eliminate(devinfo, inst, flag_live))) { inst->dst = fs_reg(spread(retype(brw_null_reg(), inst->dst.type), inst->dst.stride)); d104 1 a104 1 if (inst->dst.is_null() && can_eliminate(devinfo, inst, flag_live)) { d111 1 a111 1 const unsigned var = live_vars.var_from_reg(inst->dst); d119 1 a119 1 flag_live[0] &= ~inst->flags_written(devinfo); d122 1 a122 1 inst->remove(block, true); d128 1 a128 1 int var = live_vars.var_from_reg(inst->src[i]); a139 2 cfg->adjust_block_ips(); d144 1 a144 1 invalidate_analysis(DEPENDENCY_INSTRUCTIONS); @