head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.4 netbsd-11-0-RC3:1.1.1.4 netbsd-11-0-RC2:1.1.1.4 netbsd-11-0-RC1:1.1.1.4 netbsd-11:1.1.1.4.0.4 netbsd-11-base:1.1.1.4 netbsd-10-1-RELEASE:1.1.1.4 netbsd-9-4-RELEASE:1.1.1.2 netbsd-10-0-RELEASE:1.1.1.4 netbsd-10-0-RC6:1.1.1.4 netbsd-10-0-RC5:1.1.1.4 netbsd-10-0-RC4:1.1.1.4 netbsd-10-0-RC3:1.1.1.4 netbsd-10-0-RC2:1.1.1.4 netbsd-10-0-RC1:1.1.1.4 netbsd-10:1.1.1.4.0.2 netbsd-10-base:1.1.1.4 netbsd-9-3-RELEASE:1.1.1.2 mesa-21-3-7:1.1.1.4 netbsd-9-2-RELEASE:1.1.1.2 netbsd-9-1-RELEASE:1.1.1.2 netbsd-9-0-RELEASE:1.1.1.2 netbsd-9-0-RC2:1.1.1.2 netbsd-9-0-RC1:1.1.1.2 mesalib-19-1-7:1.1.1.3 netbsd-9:1.1.1.2.0.2 netbsd-9-base:1.1.1.2 mesa-18-3-6:1.1.1.2 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.03.10.03.42.39; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.39; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2019.06.01.07.40.59; author mrg; state Exp; branches; next 1.1.1.3; commitid HVa6uub5uYIfqspB; 1.1.1.3 date 2019.09.24.18.18.27; author maya; state Exp; branches; next 1.1.1.4; commitid KJXusGl8fi9AAhEB; 1.1.1.4 date 2022.05.09.01.23.41; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2015 Red Hat * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include "st_nir.h" #include "pipe/p_defines.h" #include "pipe/p_screen.h" #include "pipe/p_context.h" #include "program/program.h" #include "program/prog_statevars.h" #include "program/prog_parameter.h" #include "program/ir_to_mesa.h" #include "main/mtypes.h" #include "main/errors.h" #include "main/shaderapi.h" #include "main/uniforms.h" #include "st_context.h" #include "st_glsl_types.h" #include "st_program.h" #include "compiler/nir/nir.h" #include "compiler/glsl_types.h" #include "compiler/glsl/glsl_to_nir.h" #include "compiler/glsl/gl_nir.h" #include "compiler/glsl/ir.h" #include "compiler/glsl/ir_optimization.h" #include "compiler/glsl/string_to_uint_map.h" static int type_size(const struct glsl_type *type) { return type->count_attribute_slots(false); } /* Depending on PIPE_CAP_TGSI_TEXCOORD (st->needs_texcoord_semantic) we * may need to fix up varying slots so the glsl->nir path is aligned * with the anything->tgsi->nir path. */ static void st_nir_fixup_varying_slots(struct st_context *st, struct exec_list *var_list) { if (st->needs_texcoord_semantic) return; nir_foreach_variable(var, var_list) { if (var->data.location >= VARYING_SLOT_VAR0) { var->data.location += 9; } else if ((var->data.location >= VARYING_SLOT_TEX0) && (var->data.location <= VARYING_SLOT_TEX7)) { var->data.location += VARYING_SLOT_VAR0 - VARYING_SLOT_TEX0; } } } /* input location assignment for VS inputs must be handled specially, so * that it is aligned w/ st's vbo state. * (This isn't the case with, for ex, FS inputs, which only need to agree * on varying-slot w/ the VS outputs) */ static void st_nir_assign_vs_in_locations(struct gl_program *prog, nir_shader *nir) { nir->num_inputs = 0; nir_foreach_variable_safe(var, &nir->inputs) { /* NIR already assigns dual-slot inputs to two locations so all we have * to do is compact everything down. */ if (var->data.location == VERT_ATTRIB_EDGEFLAG) { /* bit of a hack, mirroring st_translate_vertex_program */ var->data.driver_location = util_bitcount64(nir->info.inputs_read); } else if (nir->info.inputs_read & BITFIELD64_BIT(var->data.location)) { var->data.driver_location = util_bitcount64(nir->info.inputs_read & BITFIELD64_MASK(var->data.location)); nir->num_inputs++; } else { /* Move unused input variables to the globals list (with no * initialization), to avoid confusing drivers looking through the * inputs array and expecting to find inputs with a driver_location * set. */ exec_node_remove(&var->node); var->data.mode = nir_var_global; exec_list_push_tail(&nir->globals, &var->node); } } } static void st_nir_assign_var_locations(struct exec_list *var_list, unsigned *size, gl_shader_stage stage) { unsigned location = 0; unsigned assigned_locations[VARYING_SLOT_TESS_MAX]; uint64_t processed_locs[2] = {0}; const int base = stage == MESA_SHADER_FRAGMENT ? (int) FRAG_RESULT_DATA0 : (int) VARYING_SLOT_VAR0; int UNUSED last_loc = 0; nir_foreach_variable(var, var_list) { const struct glsl_type *type = var->type; if (nir_is_per_vertex_io(var, stage)) { assert(glsl_type_is_array(type)); type = glsl_get_array_element(type); } unsigned var_size = type_size(type); /* Builtins don't allow component packing so we only need to worry about * user defined varyings sharing the same location. */ bool processed = false; if (var->data.location >= base) { unsigned glsl_location = var->data.location - base; for (unsigned i = 0; i < var_size; i++) { if (processed_locs[var->data.index] & ((uint64_t)1 << (glsl_location + i))) processed = true; else processed_locs[var->data.index] |= ((uint64_t)1 << (glsl_location + i)); } } /* Because component packing allows varyings to share the same location * we may have already have processed this location. */ if (processed) { unsigned driver_location = assigned_locations[var->data.location]; var->data.driver_location = driver_location; *size += type_size(type); /* An array may be packed such that is crosses multiple other arrays * or variables, we need to make sure we have allocated the elements * consecutively if the previously proccessed var was shorter than * the current array we are processing. * * NOTE: The code below assumes the var list is ordered in ascending * location order. */ assert(last_loc <= var->data.location); last_loc = var->data.location; unsigned last_slot_location = driver_location + var_size; if (last_slot_location > location) { unsigned num_unallocated_slots = last_slot_location - location; unsigned first_unallocated_slot = var_size - num_unallocated_slots; for (unsigned i = first_unallocated_slot; i < num_unallocated_slots; i++) { assigned_locations[var->data.location + i] = location; location++; } } continue; } for (unsigned i = 0; i < var_size; i++) { assigned_locations[var->data.location + i] = location + i; } var->data.driver_location = location; location += var_size; } *size += location; } static int st_nir_lookup_parameter_index(const struct gl_program_parameter_list *params, const char *name) { int loc = _mesa_lookup_parameter_index(params, name); /* is there a better way to do this? If we have something like: * * struct S { * float f; * vec4 v; * }; * uniform S color; * * Then what we get in prog->Parameters looks like: * * 0: Name=color.f, Type=6, DataType=1406, Size=1 * 1: Name=color.v, Type=6, DataType=8b52, Size=4 * * So the name doesn't match up and _mesa_lookup_parameter_index() * fails. In this case just find the first matching "color.*".. * * Note for arrays you could end up w/ color[n].f, for example. * * glsl_to_tgsi works slightly differently in this regard. It is * emitting something more low level, so it just translates the * params list 1:1 to CONST[] regs. Going from GLSL IR to TGSI, * it just calculates the additional offset of struct field members * in glsl_to_tgsi_visitor::visit(ir_dereference_record *ir) or * glsl_to_tgsi_visitor::visit(ir_dereference_array *ir). It never * needs to work backwards to get base var loc from the param-list * which already has them separated out. */ if (loc < 0) { int namelen = strlen(name); for (unsigned i = 0; i < params->NumParameters; i++) { struct gl_program_parameter *p = ¶ms->Parameters[i]; if ((strncmp(p->Name, name, namelen) == 0) && ((p->Name[namelen] == '.') || (p->Name[namelen] == '['))) { loc = i; break; } } } return loc; } static void st_nir_assign_uniform_locations(struct gl_context *ctx, struct gl_program *prog, struct gl_shader_program *shader_program, struct exec_list *uniform_list, unsigned *size) { int max = 0; int shaderidx = 0; int imageidx = 0; nir_foreach_variable(uniform, uniform_list) { int loc; /* * UBO's have their own address spaces, so don't count them towards the * number of global uniforms */ if ((uniform->data.mode == nir_var_uniform || uniform->data.mode == nir_var_shader_storage) && uniform->interface_type != NULL) continue; const struct glsl_type *type = glsl_without_array(uniform->type); if (!uniform->data.bindless && (type->is_sampler() || type->is_image())) { if (type->is_sampler()) { loc = shaderidx; shaderidx += type_size(uniform->type); } else { loc = imageidx; imageidx += type_size(uniform->type); } } else if (strncmp(uniform->name, "gl_", 3) == 0) { const gl_state_index16 *const stateTokens = uniform->state_slots[0].tokens; /* This state reference has already been setup by ir_to_mesa, but we'll * get the same index back here. */ unsigned comps; if (glsl_type_is_struct(type)) { comps = 4; } else { comps = glsl_get_vector_elements(type); } if (ctx->Const.PackedDriverUniformStorage) { loc = _mesa_add_sized_state_reference(prog->Parameters, stateTokens, comps, false); loc = prog->Parameters->ParameterValueOffset[loc]; } else { loc = _mesa_add_state_reference(prog->Parameters, stateTokens); } } else { loc = st_nir_lookup_parameter_index(prog->Parameters, uniform->name); if (ctx->Const.PackedDriverUniformStorage) { loc = prog->Parameters->ParameterValueOffset[loc]; } } uniform->data.driver_location = loc; max = MAX2(max, loc + type_size(uniform->type)); } *size = max; } void st_nir_opts(nir_shader *nir, bool scalar) { bool progress; do { progress = false; NIR_PASS_V(nir, nir_lower_vars_to_ssa); if (scalar) { NIR_PASS_V(nir, nir_lower_alu_to_scalar); NIR_PASS_V(nir, nir_lower_phis_to_scalar); } NIR_PASS_V(nir, nir_lower_alu); NIR_PASS_V(nir, nir_lower_pack); NIR_PASS(progress, nir, nir_copy_prop); NIR_PASS(progress, nir, nir_opt_remove_phis); NIR_PASS(progress, nir, nir_opt_dce); if (nir_opt_trivial_continues(nir)) { progress = true; NIR_PASS(progress, nir, nir_copy_prop); NIR_PASS(progress, nir, nir_opt_dce); } NIR_PASS(progress, nir, nir_opt_if); NIR_PASS(progress, nir, nir_opt_dead_cf); NIR_PASS(progress, nir, nir_opt_cse); NIR_PASS(progress, nir, nir_opt_peephole_select, 8); NIR_PASS(progress, nir, nir_opt_algebraic); NIR_PASS(progress, nir, nir_opt_constant_folding); NIR_PASS(progress, nir, nir_opt_undef); NIR_PASS(progress, nir, nir_opt_conditional_discard); if (nir->options->max_unroll_iterations) { NIR_PASS(progress, nir, nir_opt_loop_unroll, (nir_variable_mode)0); } } while (progress); } /* First third of converting glsl_to_nir.. this leaves things in a pre- * nir_lower_io state, so that shader variants can more easily insert/ * replace variables, etc. */ static nir_shader * st_glsl_to_nir(struct st_context *st, struct gl_program *prog, struct gl_shader_program *shader_program, gl_shader_stage stage) { const nir_shader_compiler_options *options = st->ctx->Const.ShaderCompilerOptions[prog->info.stage].NirOptions; enum pipe_shader_type type = pipe_shader_type_from_mesa(stage); struct pipe_screen *screen = st->pipe->screen; bool is_scalar = screen->get_shader_param(screen, type, PIPE_SHADER_CAP_SCALAR_ISA); assert(options); if (prog->nir) return prog->nir; nir_shader *nir = glsl_to_nir(shader_program, stage, options); /* Set the next shader stage hint for VS and TES. */ if (!nir->info.separate_shader && (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL)) { unsigned prev_stages = (1 << (prog->info.stage + 1)) - 1; unsigned stages_mask = ~prev_stages & shader_program->data->linked_stages; nir->info.next_stage = stages_mask ? (gl_shader_stage) u_bit_scan(&stages_mask) : MESA_SHADER_FRAGMENT; } else { nir->info.next_stage = MESA_SHADER_FRAGMENT; } nir_variable_mode mask = (nir_variable_mode) (nir_var_shader_in | nir_var_shader_out); nir_remove_dead_variables(nir, mask); if (options->lower_all_io_to_temps || nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_GEOMETRY) { NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, true); } else if (nir->info.stage == MESA_SHADER_FRAGMENT) { NIR_PASS_V(nir, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(nir), true, false); } NIR_PASS_V(nir, nir_lower_global_vars_to_local); NIR_PASS_V(nir, nir_split_var_copies); NIR_PASS_V(nir, nir_lower_var_copies); st_nir_opts(nir, is_scalar); return nir; } /* Second third of converting glsl_to_nir. This creates uniforms, gathers * info on varyings, etc after NIR link time opts have been applied. */ static void st_glsl_to_nir_post_opts(struct st_context *st, struct gl_program *prog, struct gl_shader_program *shader_program) { nir_shader *nir = prog->nir; /* Make a pass over the IR to add state references for any built-in * uniforms that are used. This has to be done now (during linking). * Code generation doesn't happen until the first time this shader is * used for rendering. Waiting until then to generate the parameters is * too late. At that point, the values for the built-in uniforms won't * get sent to the shader. */ nir_foreach_variable(var, &nir->uniforms) { if (strncmp(var->name, "gl_", 3) == 0) { const nir_state_slot *const slots = var->state_slots; assert(var->state_slots != NULL); const struct glsl_type *type = glsl_without_array(var->type); for (unsigned int i = 0; i < var->num_state_slots; i++) { unsigned comps; if (glsl_type_is_struct(type)) { /* Builtin struct require specical handling for now we just * make all members vec4. See st_nir_lower_builtin. */ comps = 4; } else { comps = glsl_get_vector_elements(type); } if (st->ctx->Const.PackedDriverUniformStorage) { _mesa_add_sized_state_reference(prog->Parameters, slots[i].tokens, comps, false); } else { _mesa_add_state_reference(prog->Parameters, slots[i].tokens); } } } } /* Avoid reallocation of the program parameter list, because the uniform * storage is only associated with the original parameter list. * This should be enough for Bitmap and DrawPixels constants. */ _mesa_reserve_parameter_storage(prog->Parameters, 8); /* This has to be done last. Any operation the can cause * prog->ParameterValues to get reallocated (e.g., anything that adds a * program constant) has to happen before creating this linkage. */ _mesa_associate_uniform_storage(st->ctx, shader_program, prog, true); st_set_prog_affected_state_flags(prog); NIR_PASS_V(nir, st_nir_lower_builtin); NIR_PASS_V(nir, gl_nir_lower_atomics, shader_program, true); if (st->ctx->_Shader->Flags & GLSL_DUMP) { _mesa_log("\n"); _mesa_log("NIR IR for linked %s program %d:\n", _mesa_shader_stage_to_string(prog->info.stage), shader_program->Name); nir_print_shader(nir, _mesa_get_log_file()); _mesa_log("\n\n"); } } /* TODO any better helper somewhere to sort a list? */ static void insert_sorted(struct exec_list *var_list, nir_variable *new_var) { nir_foreach_variable(var, var_list) { if (var->data.location > new_var->data.location) { exec_node_insert_node_before(&var->node, &new_var->node); return; } } exec_list_push_tail(var_list, &new_var->node); } static void sort_varyings(struct exec_list *var_list) { struct exec_list new_list; exec_list_make_empty(&new_list); nir_foreach_variable_safe(var, var_list) { exec_node_remove(&var->node); insert_sorted(&new_list, var); } exec_list_move_nodes_to(&new_list, var_list); } static void set_st_program(struct gl_program *prog, struct gl_shader_program *shader_program, nir_shader *nir) { struct st_vertex_program *stvp; struct st_common_program *stp; struct st_fragment_program *stfp; struct st_compute_program *stcp; switch (prog->info.stage) { case MESA_SHADER_VERTEX: stvp = (struct st_vertex_program *)prog; stvp->shader_program = shader_program; stvp->tgsi.type = PIPE_SHADER_IR_NIR; stvp->tgsi.ir.nir = nir; break; case MESA_SHADER_GEOMETRY: case MESA_SHADER_TESS_CTRL: case MESA_SHADER_TESS_EVAL: stp = (struct st_common_program *)prog; stp->shader_program = shader_program; stp->tgsi.type = PIPE_SHADER_IR_NIR; stp->tgsi.ir.nir = nir; break; case MESA_SHADER_FRAGMENT: stfp = (struct st_fragment_program *)prog; stfp->shader_program = shader_program; stfp->tgsi.type = PIPE_SHADER_IR_NIR; stfp->tgsi.ir.nir = nir; break; case MESA_SHADER_COMPUTE: stcp = (struct st_compute_program *)prog; stcp->shader_program = shader_program; stcp->tgsi.ir_type = PIPE_SHADER_IR_NIR; stcp->tgsi.prog = nir; break; default: unreachable("unknown shader stage"); } } static void st_nir_get_mesa_program(struct gl_context *ctx, struct gl_shader_program *shader_program, struct gl_linked_shader *shader) { struct st_context *st = st_context(ctx); struct pipe_screen *pscreen = ctx->st->pipe->screen; struct gl_program *prog; validate_ir_tree(shader->ir); prog = shader->Program; prog->Parameters = _mesa_new_parameter_list(); _mesa_copy_linked_program_data(shader_program, shader); _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader, prog->Parameters); /* Remove reads from output registers. */ if (!pscreen->get_param(pscreen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS)) lower_output_reads(shader->Stage, shader->ir); if (ctx->_Shader->Flags & GLSL_DUMP) { _mesa_log("\n"); _mesa_log("GLSL IR for linked %s program %d:\n", _mesa_shader_stage_to_string(shader->Stage), shader_program->Name); _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL); _mesa_log("\n\n"); } prog->ExternalSamplersUsed = gl_external_samplers(prog); _mesa_update_shader_textures_used(shader_program, prog); nir_shader *nir = st_glsl_to_nir(st, prog, shader_program, shader->Stage); set_st_program(prog, shader_program, nir); prog->nir = nir; } static void st_nir_link_shaders(nir_shader **producer, nir_shader **consumer, bool scalar) { nir_lower_io_arrays_to_elements(*producer, *consumer); NIR_PASS_V(*producer, nir_remove_dead_variables, nir_var_shader_out); NIR_PASS_V(*consumer, nir_remove_dead_variables, nir_var_shader_in); if (nir_remove_unused_varyings(*producer, *consumer)) { NIR_PASS_V(*producer, nir_lower_global_vars_to_local); NIR_PASS_V(*consumer, nir_lower_global_vars_to_local); /* The backend might not be able to handle indirects on * temporaries so we need to lower indirects on any of the * varyings we have demoted here. * * TODO: radeonsi shouldn't need to do this, however LLVM isn't * currently smart enough to handle indirects without causing excess * spilling causing the gpu to hang. * * See the following thread for more details of the problem: * https://lists.freedesktop.org/archives/mesa-dev/2017-July/162106.html */ nir_variable_mode indirect_mask = nir_var_local; NIR_PASS_V(*producer, nir_lower_indirect_derefs, indirect_mask); NIR_PASS_V(*consumer, nir_lower_indirect_derefs, indirect_mask); st_nir_opts(*producer, scalar); st_nir_opts(*consumer, scalar); } } extern "C" { bool st_link_nir(struct gl_context *ctx, struct gl_shader_program *shader_program) { struct st_context *st = st_context(ctx); struct pipe_screen *screen = st->pipe->screen; bool is_scalar[MESA_SHADER_STAGES]; /* Determine scalar property of each shader stage */ for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { struct gl_linked_shader *shader = shader_program->_LinkedShaders[i]; enum pipe_shader_type type; if (shader == NULL) continue; type = pipe_shader_type_from_mesa(shader->Stage); is_scalar[i] = screen->get_shader_param(screen, type, PIPE_SHADER_CAP_SCALAR_ISA); } /* Determine first and last stage. */ unsigned first = MESA_SHADER_STAGES; unsigned last = 0; for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { if (!shader_program->_LinkedShaders[i]) continue; if (first == MESA_SHADER_STAGES) first = i; last = i; } for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { struct gl_linked_shader *shader = shader_program->_LinkedShaders[i]; if (shader == NULL) continue; st_nir_get_mesa_program(ctx, shader_program, shader); nir_variable_mode mask = (nir_variable_mode) 0; if (i != first) mask = (nir_variable_mode)(mask | nir_var_shader_in); if (i != last) mask = (nir_variable_mode)(mask | nir_var_shader_out); nir_shader *nir = shader->Program->nir; if (is_scalar[i]) NIR_PASS_V(nir, nir_lower_io_to_scalar_early, mask); st_nir_opts(nir, is_scalar[i]); } /* Linking the stages in the opposite order (from fragment to vertex) * ensures that inter-shader outputs written to in an earlier stage * are eliminated if they are (transitively) not used in a later * stage. */ int next = last; for (int i = next - 1; i >= 0; i--) { struct gl_linked_shader *shader = shader_program->_LinkedShaders[i]; if (shader == NULL) continue; st_nir_link_shaders(&shader->Program->nir, &shader_program->_LinkedShaders[next]->Program->nir, is_scalar[i]); next = i; } int prev = -1; for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { struct gl_linked_shader *shader = shader_program->_LinkedShaders[i]; if (shader == NULL) continue; nir_shader *nir = shader->Program->nir; /* fragment shaders may need : */ if (nir->info.stage == MESA_SHADER_FRAGMENT) { static const gl_state_index16 wposTransformState[STATE_LENGTH] = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM }; nir_lower_wpos_ytransform_options wpos_options = { { 0 } }; struct pipe_screen *pscreen = st->pipe->screen; memcpy(wpos_options.state_tokens, wposTransformState, sizeof(wpos_options.state_tokens)); wpos_options.fs_coord_origin_upper_left = pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT); wpos_options.fs_coord_origin_lower_left = pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT); wpos_options.fs_coord_pixel_center_integer = pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER); wpos_options.fs_coord_pixel_center_half_integer = pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER); if (nir_lower_wpos_ytransform(nir, &wpos_options)) { nir_validate_shader(nir, "after nir_lower_wpos_ytransform"); _mesa_add_state_reference(shader->Program->Parameters, wposTransformState); } } NIR_PASS_V(nir, nir_lower_system_values); nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); shader->Program->info = nir->info; if (i == MESA_SHADER_VERTEX) { /* NIR expands dual-slot inputs out to two locations. We need to * compact things back down GL-style single-slot inputs to avoid * confusing the state tracker. */ shader->Program->info.inputs_read = nir_get_single_slot_attribs_mask(nir->info.inputs_read, shader->Program->DualSlotInputs); } if (prev != -1) { struct gl_program *prev_shader = shader_program->_LinkedShaders[prev]->Program; /* We can't use nir_compact_varyings with transform feedback, since * the pipe_stream_output->output_register field is based on the * pre-compacted driver_locations. */ if (!(prev_shader->sh.LinkedTransformFeedback && prev_shader->sh.LinkedTransformFeedback->NumVarying > 0)) nir_compact_varyings(shader_program->_LinkedShaders[prev]->Program->nir, nir, ctx->API != API_OPENGL_COMPAT); } prev = i; } for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { struct gl_linked_shader *shader = shader_program->_LinkedShaders[i]; if (shader == NULL) continue; st_glsl_to_nir_post_opts(st, shader->Program, shader_program); assert(shader->Program); if (!ctx->Driver.ProgramStringNotify(ctx, _mesa_shader_stage_to_program(i), shader->Program)) { _mesa_reference_program(ctx, &shader->Program, NULL); return false; } nir_sweep(shader->Program->nir); } return true; } /* Last third of preparing nir from glsl, which happens after shader * variant lowering. */ void st_finalize_nir(struct st_context *st, struct gl_program *prog, struct gl_shader_program *shader_program, nir_shader *nir) { struct pipe_screen *screen = st->pipe->screen; const nir_shader_compiler_options *options = st->ctx->Const.ShaderCompilerOptions[prog->info.stage].NirOptions; NIR_PASS_V(nir, nir_split_var_copies); NIR_PASS_V(nir, nir_lower_var_copies); if (options->lower_all_io_to_temps || nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_GEOMETRY) { NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false); } else if (nir->info.stage == MESA_SHADER_FRAGMENT) { NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, true); } if (nir->info.stage == MESA_SHADER_VERTEX) { /* Needs special handling so drvloc matches the vbo state: */ st_nir_assign_vs_in_locations(prog, nir); /* Re-lower global vars, to deal with any dead VS inputs. */ NIR_PASS_V(nir, nir_lower_global_vars_to_local); sort_varyings(&nir->outputs); st_nir_assign_var_locations(&nir->outputs, &nir->num_outputs, nir->info.stage); st_nir_fixup_varying_slots(st, &nir->outputs); } else if (nir->info.stage == MESA_SHADER_GEOMETRY || nir->info.stage == MESA_SHADER_TESS_CTRL || nir->info.stage == MESA_SHADER_TESS_EVAL) { sort_varyings(&nir->inputs); st_nir_assign_var_locations(&nir->inputs, &nir->num_inputs, nir->info.stage); st_nir_fixup_varying_slots(st, &nir->inputs); sort_varyings(&nir->outputs); st_nir_assign_var_locations(&nir->outputs, &nir->num_outputs, nir->info.stage); st_nir_fixup_varying_slots(st, &nir->outputs); } else if (nir->info.stage == MESA_SHADER_FRAGMENT) { sort_varyings(&nir->inputs); st_nir_assign_var_locations(&nir->inputs, &nir->num_inputs, nir->info.stage); st_nir_fixup_varying_slots(st, &nir->inputs); st_nir_assign_var_locations(&nir->outputs, &nir->num_outputs, nir->info.stage); } else if (nir->info.stage == MESA_SHADER_COMPUTE) { /* TODO? */ } else { unreachable("invalid shader type for tgsi bypass\n"); } NIR_PASS_V(nir, nir_lower_atomics_to_ssbo, st->ctx->Const.Program[nir->info.stage].MaxAtomicBuffers); st_nir_assign_uniform_locations(st->ctx, prog, shader_program, &nir->uniforms, &nir->num_uniforms); if (st->ctx->Const.PackedDriverUniformStorage) { NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, st_glsl_type_dword_size, (nir_lower_io_options)0); NIR_PASS_V(nir, st_nir_lower_uniforms_to_ubo); } if (screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF)) NIR_PASS_V(nir, gl_nir_lower_samplers_as_deref, shader_program); else NIR_PASS_V(nir, gl_nir_lower_samplers, shader_program); } } /* extern "C" */ @ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @initial import of mesa-18.3.6 @ text @d293 1 a293 5 /* We need to check that loc is not -1 here before accessing the * array. It can be negative for example when we have a struct that * only contains opaque types. */ if (loc >= 0 && ctx->Const.PackedDriverUniformStorage) { d299 1 @ 1.1.1.3 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @a38 1 #include "main/shaderobj.h" d51 1 d84 1 a84 1 st_nir_assign_vs_in_locations(nir_shader *nir) d106 1 a106 1 var->data.mode = nir_var_shader_temp; d243 2 a244 1 struct exec_list *uniform_list) d246 1 d257 2 a258 1 if (uniform->data.mode == nir_var_mem_ubo || uniform->data.mode == nir_var_mem_ssbo) d277 1 a277 1 if (glsl_type_is_struct_or_ifc(type)) { d303 1 d305 1 d332 1 a332 1 NIR_PASS(progress, nir, nir_opt_if, false); d335 1 a335 1 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true); a362 2 bool lower_64bit = options->lower_int64_options || options->lower_doubles_options; d367 1 a367 1 nir_shader *nir = glsl_to_nir(st->ctx, shader_program, stage, options); a383 8 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); nir_shader *softfp64 = NULL; if (nir->info.uses_64bit && (options->lower_doubles_options & nir_lower_fp64_full_software) != 0) { softfp64 = glsl_float64_funcs_to_nir(st->ctx, options); ralloc_steal(ralloc_parent(nir), softfp64); } a403 6 if (is_scalar) { NIR_PASS_V(nir, nir_lower_alu_to_scalar); } /* before buffers and vars_to_ssa */ NIR_PASS_V(nir, gl_nir_lower_bindless_images); a405 28 NIR_PASS_V(nir, gl_nir_lower_buffers, shader_program); /* Do a round of constant folding to clean up address calculations */ NIR_PASS_V(nir, nir_opt_constant_folding); if (lower_64bit) { bool lowered_64bit_ops = false; bool progress = false; NIR_PASS_V(nir, nir_opt_algebraic); do { progress = false; if (options->lower_int64_options) { NIR_PASS(progress, nir, nir_lower_int64, options->lower_int64_options); } if (options->lower_doubles_options) { NIR_PASS(progress, nir, nir_lower_doubles, softfp64, options->lower_doubles_options); } NIR_PASS(progress, nir, nir_opt_algebraic); lowered_64bit_ops |= progress; } while (progress); if (lowered_64bit_ops) st_nir_opts(nir, is_scalar); } d433 1 a433 1 if (glsl_type_is_struct_or_ifc(type)) { d464 1 a464 1 _mesa_associate_uniform_storage(st->ctx, shader_program, prog); a469 4 NIR_PASS_V(nir, nir_opt_intrinsics); nir_variable_mode mask = nir_var_function_temp; nir_remove_dead_variables(nir, mask); a592 5 if (scalar) { NIR_PASS_V(*producer, nir_lower_io_to_scalar_early, nir_var_shader_out); NIR_PASS_V(*consumer, nir_lower_io_to_scalar_early, nir_var_shader_in); } a594 6 st_nir_opts(*producer, scalar); st_nir_opts(*consumer, scalar); if (nir_link_opt_varyings(*producer, *consumer)) st_nir_opts(*consumer, scalar); d613 1 a613 1 nir_variable_mode indirect_mask = nir_var_function_temp; a619 28 /* Lowering indirects can cause varying to become unused. * nir_compact_varyings() depends on all dead varyings being removed so * we need to call nir_remove_dead_variables() again here. */ NIR_PASS_V(*producer, nir_remove_dead_variables, nir_var_shader_out); NIR_PASS_V(*consumer, nir_remove_dead_variables, nir_var_shader_in); } } static void st_lower_patch_vertices_in(struct gl_shader_program *shader_prog) { struct gl_linked_shader *linked_tcs = shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]; struct gl_linked_shader *linked_tes = shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL]; /* If we have a TCS and TES linked together, lower TES patch vertices. */ if (linked_tcs && linked_tes) { nir_shader *tcs_nir = linked_tcs->Program->nir; nir_shader *tes_nir = linked_tes->Program->nir; /* The TES input vertex count is the TCS output vertex count, * lower TES gl_PatchVerticesIn to a constant. */ uint32_t tes_patch_verts = tcs_nir->info.tess.tcs_vertices_out; NIR_PASS_V(tes_nir, nir_lower_patch_vertices, tes_patch_verts, NULL); a624 34 void st_nir_lower_wpos_ytransform(struct nir_shader *nir, struct gl_program *prog, struct pipe_screen *pscreen) { if (nir->info.stage != MESA_SHADER_FRAGMENT) return; static const gl_state_index16 wposTransformState[STATE_LENGTH] = { STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM }; nir_lower_wpos_ytransform_options wpos_options = { { 0 } }; memcpy(wpos_options.state_tokens, wposTransformState, sizeof(wpos_options.state_tokens)); wpos_options.fs_coord_origin_upper_left = pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT); wpos_options.fs_coord_origin_lower_left = pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT); wpos_options.fs_coord_pixel_center_integer = pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER); wpos_options.fs_coord_pixel_center_half_integer = pscreen->get_param(pscreen, PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER); if (nir_lower_wpos_ytransform(nir, &wpos_options)) { nir_validate_shader(nir, "after nir_lower_wpos_ytransform"); _mesa_add_state_reference(prog->Parameters, wposTransformState); } } d633 1 a633 1 unsigned last_stage = 0; d636 2 d641 19 a659 4 /* Determine scalar property of each shader stage */ enum pipe_shader_type type = pipe_shader_type_from_mesa(shader->Stage); is_scalar[i] = screen->get_shader_param(screen, type, PIPE_SHADER_CAP_SCALAR_ISA); a661 1 last_stage = i; d663 13 a675 3 if (is_scalar[i]) { NIR_PASS_V(shader->Program->nir, nir_lower_load_const_to_scalar); } d683 1 a683 1 int next = last_stage; d703 29 a731 2 NIR_PASS_V(nir, st_nir_lower_wpos_ytransform, shader->Program, st->pipe->screen); a733 1 NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays); a762 2 st_lower_patch_vertices_in(shader_program); a778 4 /* The GLSL IR won't be needed anymore. */ ralloc_free(shader->ir); shader->ir = NULL; d784 3 d788 2 a789 1 st_nir_assign_varying_locations(struct st_context *st, nir_shader *nir) d791 14 d807 1 a807 1 st_nir_assign_vs_in_locations(nir); d842 1 a842 40 unreachable("invalid shader type"); } } void st_nir_lower_samplers(struct pipe_screen *screen, nir_shader *nir, struct gl_shader_program *shader_program, struct gl_program *prog) { if (screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF)) NIR_PASS_V(nir, gl_nir_lower_samplers_as_deref, shader_program); else NIR_PASS_V(nir, gl_nir_lower_samplers, shader_program); if (prog) { prog->info.textures_used = nir->info.textures_used; prog->info.textures_used_by_txf = nir->info.textures_used_by_txf; } } /* Last third of preparing nir from glsl, which happens after shader * variant lowering. */ void st_finalize_nir(struct st_context *st, struct gl_program *prog, struct gl_shader_program *shader_program, nir_shader *nir) { struct pipe_screen *screen = st->pipe->screen; const nir_shader_compiler_options *options = st->ctx->Const.ShaderCompilerOptions[prog->info.stage].NirOptions; NIR_PASS_V(nir, nir_split_var_copies); NIR_PASS_V(nir, nir_lower_var_copies); if (options->lower_all_io_to_temps || options->lower_all_io_to_elements || nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_GEOMETRY) { NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false); } else if (nir->info.stage == MESA_SHADER_FRAGMENT) { NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, true); a844 2 st_nir_assign_varying_locations(st, nir); d848 2 a849 5 st_nir_assign_uniform_locations(st->ctx, prog, &nir->uniforms); /* Set num_uniforms in number of attribute slots (vec4s) */ nir->num_uniforms = DIV_ROUND_UP(prog->Parameters->NumParameterValues, 4); d854 1 a854 4 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, 4); } else { NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, st_glsl_uniforms_type_size, (nir_lower_io_options)0); d857 4 a860 1 st_nir_lower_samplers(screen, nir, shader_program, prog); @ 1.1.1.4 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @a33 1 #include "main/context.h" a35 1 #include "main/glspirv.h" d41 1 a42 1 #include "st_shader_cache.h" a47 1 #include "compiler/glsl/gl_nir_linker.h" a49 1 #include "compiler/glsl/linker_util.h" d63 1 a63 2 st_nir_fixup_varying_slots(struct st_context *st, nir_shader *shader, nir_variable_mode mode) d68 2 a69 5 /* This is called from finalize, but we don't want to do this adjustment twice. */ assert(!st->allow_st_finalize_nir_twice); nir_foreach_variable_with_modes(var, shader, mode) { if (var->data.location >= VARYING_SLOT_VAR0 && var->data.location < VARYING_SLOT_PATCH0) { a70 2 } else if (var->data.location == VARYING_SLOT_PNTC) { var->data.location = VARYING_SLOT_VAR8; a77 13 static void st_shader_gather_info(nir_shader *nir, struct gl_program *prog) { nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir)); /* Copy the info we just generated back into the gl_program */ const char *prog_name = prog->info.name; const char *prog_label = prog->info.label; prog->info = nir->info; prog->info.name = prog_name; prog->info.label = prog_label; } d83 2 a84 2 void st_nir_assign_vs_in_locations(struct nir_shader *nir) d86 2 a87 8 if (nir->info.stage != MESA_SHADER_VERTEX || nir->info.io_lowered) return; nir->num_inputs = util_bitcount64(nir->info.inputs_read); bool removed_inputs = false; nir_foreach_shader_in_variable_safe(var, nir) { d91 4 a94 1 if (nir->info.inputs_read & BITFIELD64_BIT(var->data.location)) { d98 1 d100 1 a100 1 /* Convert unused input variables to shader_temp (with no d105 1 d107 1 a107 1 removed_inputs = true; a109 4 /* Re-lower global vars, to deal with any dead VS inputs. */ if (removed_inputs) NIR_PASS_V(nir, nir_lower_global_vars_to_local); d112 3 a114 2 static int st_nir_lookup_parameter_index(struct gl_program *prog, nir_variable *var) d116 34 a149 1 struct gl_program_parameter_list *params = prog->Parameters; d151 36 a186 7 /* Lookup the first parameter that the uniform storage that match the * variable location. */ for (unsigned i = 0; i < params->NumParameters; i++) { int index = params->Parameters[i].MainUniformStorageIndex; if (index == var->data.location) return i; d189 8 a196 3 /* TODO: Handle this fallback for SPIR-V. We need this for GLSL e.g. in * dEQP-GLES2.functional.uniform_api.random.3 */ d225 2 a226 2 if (!prog->sh.data->spirv) { int namelen = strlen(var->name); d229 1 a229 1 if ((strncmp(p->Name, var->name, namelen) == 0) && d231 2 a232 1 return i; d237 1 a237 1 return -1; d243 1 a243 1 nir_shader *nir) d248 1 a248 1 nir_foreach_uniform_variable(uniform, nir) { d251 7 d267 1 a267 1 } else if (uniform->state_slots) { d283 1 a283 1 loc = prog->Parameters->Parameters[loc].ValueOffset; d288 1 a288 1 loc = st_nir_lookup_parameter_index(prog, uniform); d295 1 a295 1 loc = prog->Parameters->Parameters[loc].ValueOffset; d304 1 a304 1 st_nir_opts(nir_shader *nir) a306 1 d311 4 a314 18 /* Linking deals with unused inputs/outputs, but here we can remove * things local to the shader in the hopes that we can cleanup other * things. This pass will also remove variables with only stores, so we * might be able to make progress after it. */ NIR_PASS(progress, nir, nir_remove_dead_variables, nir_var_function_temp | nir_var_shader_temp | nir_var_mem_shared, NULL); NIR_PASS(progress, nir, nir_opt_copy_prop_vars); NIR_PASS(progress, nir, nir_opt_dead_write_vars); if (nir->options->lower_to_scalar) { NIR_PASS_V(nir, nir_lower_alu_to_scalar, nir->options->lower_to_scalar_filter, NULL); NIR_PASS_V(nir, nir_lower_phis_to_scalar, false); a331 1 NIR_PASS(progress, nir, nir_opt_phi_precision); a334 25 if (!nir->info.flrp_lowered) { unsigned lower_flrp = (nir->options->lower_flrp16 ? 16 : 0) | (nir->options->lower_flrp32 ? 32 : 0) | (nir->options->lower_flrp64 ? 64 : 0); if (lower_flrp) { bool lower_flrp_progress = false; NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp, lower_flrp, false /* always_precise */); if (lower_flrp_progress) { NIR_PASS(progress, nir, nir_opt_constant_folding); progress = true; } } /* Nothing should rematerialize any flrps, so we only need to do this * lowering once. */ nir->info.flrp_lowered = true; } d338 1 a338 1 NIR_PASS(progress, nir, nir_opt_loop_unroll); a342 12 static void shared_type_info(const struct glsl_type *type, unsigned *size, unsigned *align) { assert(glsl_type_is_vector_or_scalar(type)); uint32_t comp_size = glsl_type_is_boolean(type) ? 4 : glsl_get_bit_size(type) / 8; unsigned length = glsl_get_vector_elements(type); *size = comp_size * length, *align = comp_size * (length == 3 ? 4 : length); } d347 4 a350 4 static void st_nir_preprocess(struct st_context *st, struct gl_program *prog, struct gl_shader_program *shader_program, gl_shader_stage stage) a351 1 struct pipe_screen *screen = st->screen; d354 3 d358 7 a364 1 nir_shader *nir = prog->nir; d382 2 a383 1 if (!st->ctx->SoftFP64 && ((nir->info.bit_sizes_int | nir->info.bit_sizes_float) & 64) && d385 2 a386 1 st->ctx->SoftFP64 = glsl_float64_funcs_to_nir(st->ctx, options); d389 3 a391 9 /* ES has strict SSO validation rules for shader IO matching so we can't * remove dead IO until the resource list has been built. Here we skip * removing them until later. This will potentially make the IO lowering * calls below do a little extra work but should otherwise have no impact. */ if (!_mesa_is_gles(st->ctx) || !nir->info.separate_shader) { nir_variable_mode mask = nir_var_shader_in | nir_var_shader_out; nir_remove_dead_variables(nir, mask, NULL); } d399 1 a399 2 } else if (nir->info.stage == MESA_SHADER_FRAGMENT || !screen->get_param(screen, PIPE_CAP_TGSI_CAN_READ_OUTPUTS)) { d409 2 a410 3 if (options->lower_to_scalar) { NIR_PASS_V(nir, nir_lower_alu_to_scalar, options->lower_to_scalar_filter, NULL); d414 2 a415 10 NIR_PASS_V(nir, gl_nir_lower_images, true); /* TODO: Change GLSL to not lower shared memory. */ if (prog->nir->info.stage == MESA_SHADER_COMPUTE && shader_program->data->spirv) { NIR_PASS_V(prog->nir, nir_lower_vars_to_explicit_types, nir_var_mem_shared, shared_type_info); NIR_PASS_V(prog->nir, nir_lower_explicit_io, nir_var_mem_shared, nir_address_format_32bit_offset); } d417 1 a419 1 } d421 19 a439 10 static bool dest_is_64bit(nir_dest *dest, void *state) { bool *lower = (bool *)state; if (dest && (nir_dest_bit_size(*dest) == 64)) { *lower = true; return false; } return true; } d441 2 a442 7 static bool src_is_64bit(nir_src *src, void *state) { bool *lower = (bool *)state; if (src && (nir_src_bit_size(*src) == 64)) { *lower = true; return false; a443 2 return true; } d445 1 a445 13 static bool filter_64_bit_instr(const nir_instr *const_instr, UNUSED const void *data) { bool lower = false; /* lower_alu_to_scalar required nir_instr to be const, but nir_foreach_* * doesn't have const variants, so do the ugly const_cast here. */ nir_instr *instr = const_cast(const_instr); nir_foreach_dest(instr, dest_is_64bit, &lower); if (lower) return true; nir_foreach_src(instr, src_is_64bit, &lower); return lower; d451 1 a451 1 static char * a455 1 struct pipe_screen *screen = st->screen; d464 5 a468 3 nir_foreach_uniform_variable(var, nir) { const nir_state_slot *const slots = var->state_slots; if (slots != NULL) { d473 4 a476 1 comps = _mesa_program_state_value_size(slots[i].tokens); d497 1 a497 3 _mesa_ensure_and_associate_uniform_storage(st->ctx, shader_program, prog, 16); st_set_prog_affected_state_flags(prog); d499 3 a501 3 /* None of the builtins being lowered here can be produced by SPIR-V. See * _mesa_builtin_uniform_desc. Also drivers that support packed uniform * storage don't need to lower builtins. d503 1 a503 10 if (!shader_program->data->spirv && !st->ctx->Const.PackedDriverUniformStorage) { /* at this point, array uniforms have been split into separate * nir_variable structs where possible. this codepath can't handle dynamic * array indexing, however, so all indirect uniform derefs * must be eliminated beforehand to avoid trying to lower one of those builtins */ NIR_PASS_V(nir, nir_lower_indirect_builtin_uniform_derefs); NIR_PASS_V(nir, st_nir_lower_builtin); } d505 1 a505 2 if (!screen->get_param(screen, PIPE_CAP_NIR_ATOMICS_AS_DEREF)) NIR_PASS_V(nir, gl_nir_lower_atomics, shader_program, true); d507 2 a509 1 NIR_PASS_V(nir, nir_opt_fragdepth); d511 2 a512 40 /* Lower 64-bit ops. */ if (nir->options->lower_int64_options || nir->options->lower_doubles_options) { bool lowered_64bit_ops = false; bool revectorize = false; /* nir_lower_doubles is not prepared for vector ops, so if the backend doesn't * request lower_alu_to_scalar until now, lower all 64 bit ops, and try to * vectorize them afterwards again */ if (!nir->options->lower_to_scalar) { NIR_PASS(revectorize, nir, nir_lower_alu_to_scalar, filter_64_bit_instr, nullptr); NIR_PASS(revectorize, nir, nir_lower_phis_to_scalar, false); } if (nir->options->lower_doubles_options) { NIR_PASS(lowered_64bit_ops, nir, nir_lower_doubles, st->ctx->SoftFP64, nir->options->lower_doubles_options); } if (nir->options->lower_int64_options) NIR_PASS(lowered_64bit_ops, nir, nir_lower_int64); if (revectorize) NIR_PASS_V(nir, nir_opt_vectorize, nullptr, nullptr); if (revectorize || lowered_64bit_ops) st_nir_opts(nir); } nir_variable_mode mask = nir_var_shader_in | nir_var_shader_out | nir_var_function_temp; nir_remove_dead_variables(nir, mask, NULL); if (!st->has_hw_atomics && !screen->get_param(screen, PIPE_CAP_NIR_ATOMICS_AS_DEREF)) NIR_PASS_V(nir, nir_lower_atomics_to_ssbo); st_finalize_nir_before_variants(nir); char *msg = NULL; if (st->allow_st_finalize_nir_twice) msg = st_finalize_nir(st, prog, shader_program, nir, true, true); d522 3 d526 10 a535 1 return msg; d539 1 a539 1 st_nir_vectorize_io(nir_shader *producer, nir_shader *consumer) d541 5 a545 16 NIR_PASS_V(producer, nir_lower_io_to_vector, nir_var_shader_out); NIR_PASS_V(producer, nir_opt_combine_stores, nir_var_shader_out); NIR_PASS_V(consumer, nir_lower_io_to_vector, nir_var_shader_in); if ((producer)->info.stage != MESA_SHADER_TESS_CTRL) { /* Calling lower_io_to_vector creates output variable writes with * write-masks. We only support these for TCS outputs, so for other * stages, we need to call nir_lower_io_to_temporaries to get rid of * them. This, in turn, creates temporary variables and extra * copy_deref intrinsics that we need to clean up. */ NIR_PASS_V(producer, nir_lower_io_to_temporaries, nir_shader_get_entrypoint(producer), true, false); NIR_PASS_V(producer, nir_lower_global_vars_to_local); NIR_PASS_V(producer, nir_split_var_copies); NIR_PASS_V(producer, nir_lower_var_copies); d547 2 d550 40 a589 6 /* Undef scalar store_deref intrinsics are not ignored by nir_lower_io, * so they must be removed before that. These passes remove them. */ NIR_PASS_V(producer, nir_lower_vars_to_ssa); NIR_PASS_V(producer, nir_opt_undef); NIR_PASS_V(producer, nir_opt_dce); d593 3 a595 1 st_nir_link_shaders(nir_shader *producer, nir_shader *consumer) d597 25 a621 3 if (producer->options->lower_to_scalar) { NIR_PASS_V(producer, nir_lower_io_to_scalar_early, nir_var_shader_out); NIR_PASS_V(consumer, nir_lower_io_to_scalar_early, nir_var_shader_in); d624 2 a625 1 nir_lower_io_arrays_to_elements(producer, consumer); d627 1 a627 2 st_nir_opts(producer); st_nir_opts(consumer); d629 3 a631 2 if (nir_link_opt_varyings(producer, consumer)) st_nir_opts(consumer); d633 35 a667 2 NIR_PASS_V(producer, nir_remove_dead_variables, nir_var_shader_out, NULL); NIR_PASS_V(consumer, nir_remove_dead_variables, nir_var_shader_in, NULL); d669 2 a670 3 if (nir_remove_unused_varyings(producer, consumer)) { NIR_PASS_V(producer, nir_lower_global_vars_to_local); NIR_PASS_V(consumer, nir_lower_global_vars_to_local); d672 2 a673 2 st_nir_opts(producer); st_nir_opts(consumer); d675 1 a675 1 /* Optimizations can cause varyings to become unused. d679 2 a680 4 NIR_PASS_V(producer, nir_remove_dead_variables, nir_var_shader_out, NULL); NIR_PASS_V(consumer, nir_remove_dead_variables, nir_var_shader_in, NULL); a681 2 nir_link_varying_precision(producer, consumer); d716 1 a716 1 STATE_FB_WPOS_Y_TRANSFORM a738 8 static const gl_state_index16 pntcTransformState[STATE_LENGTH] = { STATE_FB_PNTC_Y_TRANSFORM }; if (nir_lower_pntc_ytransform(nir, &pntcTransformState)) { _mesa_add_state_reference(prog->Parameters, pntcTransformState); } d746 2 a747 2 struct gl_linked_shader *linked_shader[MESA_SHADER_STAGES]; unsigned num_shaders = 0; d749 1 d751 8 a758 3 if (shader_program->_LinkedShaders[i]) linked_shader[num_shaders++] = shader_program->_LinkedShaders[i]; } d760 2 a761 12 for (unsigned i = 0; i < num_shaders; i++) { struct gl_linked_shader *shader = linked_shader[i]; const nir_shader_compiler_options *options = st->ctx->Const.ShaderCompilerOptions[shader->Stage].NirOptions; struct gl_program *prog = shader->Program; struct st_program *stp = (struct st_program *)prog; _mesa_copy_linked_program_data(shader_program, shader); assert(!prog->nir); stp->shader_program = shader_program; stp->state.type = PIPE_SHADER_IR_NIR; d763 1 a763 23 /* Parameters will be filled during NIR linking. */ prog->Parameters = _mesa_new_parameter_list(); if (shader_program->data->spirv) { prog->nir = _mesa_spirv_to_nir(ctx, shader_program, shader->Stage, options); } else { validate_ir_tree(shader->ir); if (ctx->_Shader->Flags & GLSL_DUMP) { _mesa_log("\n"); _mesa_log("GLSL IR for linked %s program %d:\n", _mesa_shader_stage_to_string(shader->Stage), shader_program->Name); _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL); _mesa_log("\n\n"); } prog->nir = glsl_to_nir(st->ctx, shader_program, shader->Stage, options); } st_nir_preprocess(st, prog, shader_program, shader->Stage); if (options->lower_to_scalar) { a767 2 st_lower_patch_vertices_in(shader_program); d773 10 a782 20 for (int i = num_shaders - 2; i >= 0; i--) { st_nir_link_shaders(linked_shader[i]->Program->nir, linked_shader[i + 1]->Program->nir); } /* Linking shaders also optimizes them. Separate shaders, compute shaders * and shaders with a fixed-func VS or FS that don't need linking are * optimized here. */ if (num_shaders == 1) st_nir_opts(linked_shader[0]->Program->nir); if (shader_program->data->spirv) { static const gl_nir_linker_options opts = { true /*fill_parameters */ }; if (!gl_nir_link_spirv(ctx, shader_program, &opts)) return GL_FALSE; } else { if (!gl_nir_link_glsl(ctx, shader_program)) return GL_FALSE; d785 5 a789 5 for (unsigned i = 0; i < num_shaders; i++) { struct gl_program *prog = linked_shader[i]->Program; prog->ExternalSamplersUsed = gl_external_samplers(prog); _mesa_update_shader_textures_used(shader_program, prog); } a790 5 nir_build_program_resource_list(ctx, shader_program, shader_program->data->spirv); for (unsigned i = 0; i < num_shaders; i++) { struct gl_linked_shader *shader = linked_shader[i]; a792 21 /* don't infer ACCESS_NON_READABLE so that Program->sh.ImageAccess is * correct: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3278 */ nir_opt_access_options opt_access_options; opt_access_options.is_vulkan = false; opt_access_options.infer_non_readable = false; NIR_PASS_V(nir, nir_opt_access, &opt_access_options); /* This needs to run after the initial pass of nir_lower_vars_to_ssa, so * that the buffer indices are constants in nir where they where * constants in GLSL. */ NIR_PASS_V(nir, gl_nir_lower_buffers, shader_program); /* Remap the locations to slots so those requiring two slots will occupy * two locations. For instance, if we have in the IR code a dvec3 attr0 in * location 0 and vec4 attr1 in location 1, in NIR attr0 will use * locations/slots 0 and 1, and attr1 will use location/slot 2 */ if (nir->info.stage == MESA_SHADER_VERTEX && !shader_program->data->spirv) nir_remap_dual_slot_attributes(nir, &shader->Program->DualSlotInputs); d794 1 a794 1 st->screen); a796 2 NIR_PASS_V(nir, nir_lower_compute_system_values, NULL); d799 3 a801 2 st_shader_gather_info(nir, shader->Program); if (shader->Stage == MESA_SHADER_VERTEX) { d811 3 a813 2 if (i >= 1) { struct gl_program *prev_shader = linked_shader[i - 1]->Program; d821 2 a822 5 nir_compact_varyings(prev_shader->nir, nir, ctx->API != API_OPENGL_COMPAT); if (ctx->Const.ShaderCompilerOptions[shader->Stage].NirOptions->vectorize_io) st_nir_vectorize_io(prev_shader->nir, nir); d824 1 d827 1 a827 1 struct shader_info *prev_info = NULL; d829 4 a832 9 for (unsigned i = 0; i < num_shaders; i++) { struct gl_linked_shader *shader = linked_shader[i]; struct shader_info *info = &shader->Program->nir->info; char *msg = st_glsl_to_nir_post_opts(st, shader->Program, shader_program); if (msg) { linker_error(shader_program, msg); break; } d834 1 a834 6 if (prev_info && ctx->Const.ShaderCompilerOptions[shader->Stage].NirOptions->unify_interfaces) { prev_info->outputs_written |= info->inputs_read & ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER); info->inputs_read |= prev_info->outputs_written & ~(VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER); d836 6 a841 2 prev_info->patch_outputs_written |= info->patch_inputs_read; info->patch_inputs_read |= prev_info->patch_outputs_written; a842 2 prev_info = info; } d844 1 a844 32 for (unsigned i = 0; i < num_shaders; i++) { struct gl_linked_shader *shader = linked_shader[i]; struct gl_program *prog = shader->Program; struct st_program *stp = st_program(prog); /* Make sure that prog->info is in sync with nir->info, but st/mesa * expects some of the values to be from before lowering. */ shader_info old_info = prog->info; prog->info = prog->nir->info; prog->info.name = old_info.name; prog->info.label = old_info.label; prog->info.num_ssbos = old_info.num_ssbos; prog->info.num_ubos = old_info.num_ubos; prog->info.num_abos = old_info.num_abos; if (prog->info.stage == MESA_SHADER_VERTEX) prog->info.inputs_read = old_info.inputs_read; /* Initialize st_vertex_program members. */ if (shader->Stage == MESA_SHADER_VERTEX) st_prepare_vertex_program(stp, NULL); /* Get pipe_stream_output_info. */ if (shader->Stage == MESA_SHADER_VERTEX || shader->Stage == MESA_SHADER_TESS_EVAL || shader->Stage == MESA_SHADER_GEOMETRY) st_translate_stream_output_info(prog); st_store_ir_in_disk_cache(st, prog, true); st_release_variants(st, stp); st_finalize_program(st, prog); d858 7 a864 1 nir_assign_io_var_locations(nir, nir_var_shader_out, d867 1 a867 1 st_nir_fixup_varying_slots(st, nir, nir_var_shader_out); d871 2 a872 1 nir_assign_io_var_locations(nir, nir_var_shader_in, d875 1 a875 1 st_nir_fixup_varying_slots(st, nir, nir_var_shader_in); d877 2 a878 1 nir_assign_io_var_locations(nir, nir_var_shader_out, d881 1 a881 1 st_nir_fixup_varying_slots(st, nir, nir_var_shader_out); d883 2 a884 1 nir_assign_io_var_locations(nir, nir_var_shader_in, d887 2 a888 2 st_nir_fixup_varying_slots(st, nir, nir_var_shader_in); nir_assign_io_var_locations(nir, nir_var_shader_out, d909 2 a910 3 BITSET_COPY(prog->info.textures_used, nir->info.textures_used); BITSET_COPY(prog->info.textures_used_by_txf, nir->info.textures_used_by_txf); prog->info.images_used = nir->info.images_used; a913 31 static int st_packed_uniforms_type_size(const struct glsl_type *type, bool bindless) { return glsl_count_dword_slots(type, bindless); } static int st_unpacked_uniforms_type_size(const struct glsl_type *type, bool bindless) { return glsl_count_vec4_slots(type, false, bindless); } void st_nir_lower_uniforms(struct st_context *st, nir_shader *nir) { if (st->ctx->Const.PackedDriverUniformStorage) { NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, st_packed_uniforms_type_size, (nir_lower_io_options)0); } else { NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, st_unpacked_uniforms_type_size, (nir_lower_io_options)0); } if (nir->options->lower_uniforms_to_ubo) NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, st->ctx->Const.PackedDriverUniformStorage, !st->ctx->Const.NativeIntegers); } d917 1 a917 1 char * d919 1 a919 3 struct gl_shader_program *shader_program, nir_shader *nir, bool finalize_by_driver, bool is_before_variants) d921 3 a923 1 struct pipe_screen *screen = st->screen; d927 8 d936 1 a936 4 if (st->lower_rect_tex) { struct nir_lower_tex_options opts = { 0 }; opts.lower_rect = true; d938 2 a939 2 NIR_PASS_V(nir, nir_lower_tex, &opts); } d941 2 a942 2 st_nir_assign_varying_locations(st, nir); st_nir_assign_uniform_locations(st->ctx, prog, nir); d947 7 a953 8 st_nir_lower_uniforms(st, nir); if (is_before_variants && nir->options->lower_uniforms_to_ubo) { /* This must be done after uniforms are lowered to UBO and all * nir_var_uniform variables are removed from NIR to prevent conflicts * between state parameter merging and shader variant generation. */ _mesa_optimize_state_parameters(&st->ctx->Const, prog->Parameters); a956 8 if (!screen->get_param(screen, PIPE_CAP_NIR_IMAGES_AS_DEREF)) NIR_PASS_V(nir, gl_nir_lower_images, false); char *msg = NULL; if (finalize_by_driver && screen->finalize_nir) msg = screen->finalize_nir(screen, nir); return msg; @