head	1.14;
access;
symbols
	pkgsrc-2026Q1:1.14.0.2
	pkgsrc-2026Q1-base:1.14
	pkgsrc-2025Q4:1.13.0.4
	pkgsrc-2025Q4-base:1.13
	pkgsrc-2025Q3:1.13.0.2
	pkgsrc-2025Q3-base:1.13
	pkgsrc-2025Q2:1.12.0.2
	pkgsrc-2025Q2-base:1.12
	pkgsrc-2025Q1:1.11.0.4
	pkgsrc-2025Q1-base:1.11
	pkgsrc-2024Q4:1.11.0.2
	pkgsrc-2024Q4-base:1.11
	pkgsrc-2024Q3:1.10.0.2
	pkgsrc-2024Q3-base:1.10
	pkgsrc-2024Q2:1.8.0.2
	pkgsrc-2024Q2-base:1.8
	pkgsrc-2024Q1:1.7.0.10
	pkgsrc-2024Q1-base:1.7
	pkgsrc-2023Q4:1.7.0.8
	pkgsrc-2023Q4-base:1.7
	pkgsrc-2023Q3:1.7.0.6
	pkgsrc-2023Q3-base:1.7
	pkgsrc-2023Q2:1.7.0.4
	pkgsrc-2023Q2-base:1.7
	pkgsrc-2023Q1:1.7.0.2
	pkgsrc-2023Q1-base:1.7
	pkgsrc-2022Q4:1.6.0.6
	pkgsrc-2022Q4-base:1.6
	pkgsrc-2022Q3:1.6.0.4
	pkgsrc-2022Q3-base:1.6
	pkgsrc-2022Q2:1.6.0.2
	pkgsrc-2022Q2-base:1.6
	pkgsrc-2022Q1:1.5.0.2
	pkgsrc-2022Q1-base:1.5
	pkgsrc-2021Q4:1.4.0.2
	pkgsrc-2021Q4-base:1.4
	pkgsrc-2021Q3:1.2.0.4
	pkgsrc-2021Q3-base:1.2
	pkgsrc-2021Q2:1.2.0.2
	pkgsrc-2021Q2-base:1.2
	pkgsrc-2021Q1:1.1.0.12
	pkgsrc-2021Q1-base:1.1
	pkgsrc-2020Q4:1.1.0.10
	pkgsrc-2020Q4-base:1.1
	pkgsrc-2020Q3:1.1.0.8
	pkgsrc-2020Q3-base:1.1
	pkgsrc-2020Q2:1.1.0.6
	pkgsrc-2020Q2-base:1.1
	pkgsrc-2020Q1:1.1.0.2
	pkgsrc-2020Q1-base:1.1
	pkgsrc-2019Q4:1.1.0.4
	pkgsrc-2019Q4-base:1.1;
locks; strict;
comment	@# @;


1.14
date	2025.12.27.16.31.08;	author ryoon;	state Exp;
branches;
next	1.13;
commitid	EZkDYhoFCdS9b4oG;

1.13
date	2025.08.03.15.39.41;	author ryoon;	state Exp;
branches;
next	1.12;
commitid	JuNTTyi27kKtAi5G;

1.12
date	2025.06.14.05.49.50;	author ryoon;	state Exp;
branches;
next	1.11;
commitid	3lDMtwWr7KpMVOYF;

1.11
date	2024.10.17.09.28.08;	author wiz;	state Exp;
branches;
next	1.10;
commitid	7aTAUOwHoSLXQZtF;

1.10
date	2024.09.18.06.23.15;	author wiz;	state Exp;
branches;
next	1.9;
commitid	GRMwngQlkmFiLfqF;

1.9
date	2024.08.10.02.32.59;	author ryoon;	state Exp;
branches;
next	1.8;
commitid	j91jizGc62h4KdlF;

1.8
date	2024.06.05.17.16.08;	author ryoon;	state Exp;
branches;
next	1.7;
commitid	isPavoQsO9fzKOcF;

1.7
date	2023.01.24.14.32.20;	author ryoon;	state Exp;
branches;
next	1.6;
commitid	tUES2qTIFzdQQNaE;

1.6
date	2022.05.19.15.59.04;	author ryoon;	state Exp;
branches;
next	1.5;
commitid	8G49BBUA0sdPmGED;

1.5
date	2022.01.04.20.52.35;	author wiz;	state Exp;
branches;
next	1.4;
commitid	CYyhdK9qtoffkmnD;

1.4
date	2021.12.16.12.49.12;	author wiz;	state Exp;
branches;
next	1.3;
commitid	P4iRJ07exAeBgSkD;

1.3
date	2021.11.21.15.10.08;	author ryoon;	state Exp;
branches;
next	1.2;
commitid	OajZRI9a2ktFQFhD;

1.2
date	2021.04.14.13.43.57;	author ryoon;	state Exp;
branches;
next	1.1;
commitid	zIwAmi9d6EgCtgPC;

1.1
date	2019.10.05.06.19.15;	author ryoon;	state Exp;
branches;
next	;
commitid	1XNR7SV72J99VDFB;


desc
@@


1.14
log
@cad/py-PyRTL: Fix the error from render_trace() on Jupyter

* Do not fail with 'Javascript Error: $ is not defined'.
* Bump PKGREVISION.
@
text
@# $NetBSD: Makefile,v 1.13 2025/08/03 15:39:41 ryoon Exp $

DISTNAME=	pyrtl-${PKGVERSION_NOREV}
PKGNAME=	${PYPKGPREFIX}-PyRTL-0.12
PKGREVISION=	1
CATEGORIES=	cad python
MASTER_SITES=	${MASTER_SITE_PYPI:=p/pyrtl/}

MAINTAINER=	ryoon@@NetBSD.org
HOMEPAGE=	https://ucsbarchlab.github.io/PyRTL/
COMMENT=	Register-transfer-level hardware design and simulation
LICENSE=	modified-bsd

TOOL_DEPENDS+=	${PYPKGPREFIX}-hatchling-[0-9]*:../../devel/py-hatchling
DEPENDS+=	${PYPKGPREFIX}-six-[0-9]*:../../lang/py-six

# as of 0.11.2
# 2 failed, 1176 passed, 9 skipped

USE_LANGUAGES=	c # for test

pre-configure:
	cd ${WRKSRC} && ${RM} pyrtl/*.orig

# for tests
.include "../../lang/python/tool.mk"
.include "../../lang/python/wheel.mk"
.include "../../mk/bsd.pkg.mk"
@


1.13
log
@cad/py-PyRTL: Update to 0.12

Changelog:
0.12 - 2025-07-28
Added

    GateGraph is an alternative PyRTL logic representation, designed to simplify analysis.

Changed

    Rewrote output_to_verilog and output_verilog_testbench. The new implementation's output should be much easier to read:
        Single-use expressions are inlined.
        Try mangling unusable WireVector and MemBlock names first, before assigning them entirely new names.
        Add comments to the generated Verilog that show the un-mangled names.
    Many documentation improvements:
        Most methods and functions now have examples.
        Consistently use canonical top-level pyrtl.* names, rather than module-level names (pyrtl.WireVector, not pyrtl.wire.WireVector).
        Enabled intersphinx for clickable standard library references (list, dict, etc).
        Set up doctest for examples, to verify that documentation examples still work.
    Switched from pylint and pycodestyle to ruff:
        Applied many ruff fixes.
        Reformatted the code with ruff format.
        Updated tox to run ruff check and ruff format.

Removed

    Removed remaining Python 2 support.

Fixed

    Fixed XOR implementation in and_inverter_synth pass (@@EdwinChang24)
    output_verilog_testbench should not re-initialize RomBlocks.
    FastSimulation was not setting init_memvalue correctly (renamed to SimulationTrace.memory_value_map).
    Specify bitwidths for Verilog initial register and memory values. They were previously unsized constants, which are implicitly 32-bit signed, which could cause surprises.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.12 2025/06/14 05:49:50 ryoon Exp $
d5 1
d22 3
@


1.12
log
@cad/py-PyRTL: Update to 0.11.3

Changelog:
## [0.11.3] - 2025-06-12

### Added

- An optimization pass to [optimize inverter chains](https://github.com/UCSBarchlab/PyRTL/blob/d5f8dbe53f54e61e1d54722449e4894b885243c7/pyrtl/passes.py#L130)
- `one_hot_to_binary` encoder ([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.helperfuncs.one_hot_to_binary))
- `binary_to_one_hot` decoder ([documentation](https://pyrtl.readthedocs.io/en/latest/helpers.html#pyrtl.helperfuncs.binary_to_one_hot))

### Changed

- More support for signed integers: Signed integers can now be used in `RomBlock`'s
  `romdata`, `Simulation`'s `mem_value_map`, and Verilog-style register reset values.
- Improved documentation:
  - [conditional_assignment](https://pyrtl.readthedocs.io/en/latest/basic.html#module-pyrtl.conditional)
  - [WireVector equality](https://pyrtl.readthedocs.io/en/latest/basic.html#wirevector-equality)

### Fixed

- Use iteration instead of recursion to avoid stack overflow in `find_producer`.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.11 2024/10/17 09:28:08 wiz Exp $
d4 1
a4 1
PKGNAME=	${PYPKGPREFIX}-PyRTL-0.11.3
@


1.11
log
@py-PyRTL: remove unused test dependencies
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.10 2024/09/18 06:23:15 wiz Exp $
d4 1
a4 1
PKGNAME=	${PYPKGPREFIX}-PyRTL-0.11.2
@


1.10
log
@py-PyRTL: add missing tool dependency

Fix testing and add test status.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.9 2024/08/10 02:32:59 ryoon Exp $
a17 3
# 'make test' fails with 2 arithmetic FAILs.
TEST_DEPENDS+=	${PYPKGPREFIX}-tox-[0-9]*:../../devel/py-tox
TEST_DEPENDS+=	${PYPKGPREFIX}-nose-[0-9]*:../../devel/py-nose
@


1.9
log
@cad/py-PyRTL: Update to 0.11.2

Changelog:
### Added

- Added an `initialize_registers` option to `output_to_verilog`
  documentation

### Changed

- Improved handling of signed integers.

### Fixed

- Fixed a `wire_matrix` bug involving single-element matrices of `Inputs` or `Registers`.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.8 2024/06/05 17:16:08 ryoon Exp $
d13 1
d16 2
d24 2
a25 2
PYTHON_VERSIONS_INCOMPATIBLE=	27

@


1.8
log
@cad/py-PyRTL: Update to 0.11.1

Changelog:
0.11.1:
Upgrade download-artifact action to v4, for compatibility with upload

-artifact v4.


0.11.0:
Set PyRTL's Python package version from `git tag`.

This avoid keeping the latest version number in two places, `pyproject.toml`
and `git tag`. Simplify instructions in release/README.md.

Rename some GitHub workflow jobs to clarify their purpose.


0.11.0rc1:
GitHub actions to automate PyRTL releases to TestPyPI and PyPI.

- Migrade from `setup.{py,cfg}` to `pyproject.toml`
- Add `python-release.yml` workflow
- Prepare a `0.11.0rc1` release.
- Rename `python-package.yml` to `python-test.yml` and upgrade checkout action to `v4`.
- Add release documentation at `release/README.md`
- Use latest python and ubuntu versions for readthedocs.
- Remove the release version number from the sphinx configuration
  (`docs/conf.py`). It doesn't seem to do anything.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.7 2023/01/24 14:32:20 ryoon Exp $
d4 1
a4 1
PKGNAME=	${PYPKGPREFIX}-PyRTL-0.11.1
@


1.7
log
@py-PyRTL: Update to 0.10.2

Changelog:
* Fix tox tests on Apple M1, aarch64.
* Fix another tox tests.
* Fix error message typo.
* Support newer graphviz to generate SVG.
* Fix constant propagation for synthesized blocks.
* Improve net_connections() function.
* Improve paths() function.
* Update documentation.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.6 2022/05/19 15:59:04 ryoon Exp $
d4 1
a4 1
PKGNAME=	${PYPKGPREFIX}-PyRTL-0.10.2
a20 2
EGG_NAME=	${DISTNAME:tl}

d23 1
a23 1
.include "../../lang/python/egg.mk"
@


1.6
log
@py-PyRTL: Support graphics/py-graphviz-0.19 or later too
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.5 2022/01/04 20:52:35 wiz Exp $
d4 1
a4 2
PKGNAME=	${PYPKGPREFIX}-PyRTL-0.10.1
PKGREVISION=	2
@


1.5
log
@*: bump PKGREVISION for egg.mk users

They now have a tool dependency on py-setuptools instead of a DEPENDS
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.4 2021/12/16 12:49:12 wiz Exp $
d5 1
a5 1
PKGREVISION=	1
@


1.4
log
@py-PyRTL: mark as not for python 2.7
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.3 2021/11/21 15:10:08 ryoon Exp $
d5 1
@


1.3
log
@py-PyRTL: Update to 0.10.1

Changelog:
0.10.1
Various fixes to import/export and visualization.

0.10
Not provided as summary.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.2 2021/04/14 13:43:57 ryoon Exp $
d23 2
@


1.2
log
@py-PyRTL: Update to 0.9.0

* Use PyPI as MASTER_SITES.
  0.9.0 is not released on GitHub.

Changelog:
Not available.
@
text
@d1 1
a1 1
# $NetBSD: Makefile,v 1.1 2019/10/05 06:19:15 ryoon Exp $
d4 1
a4 1
PKGNAME=	${PYPKGPREFIX}-PyRTL-0.9.0
@


1.1
log
@cad/py-PyRTL: import py37-PyRTL-0.8.7

PyRTL provides a collection of classes for pythonic register-transfer
level design, simulation, tracing, and testing suitable for teaching
and research. Simplicity, usability, clarity, and extensibility
rather than performance or optimization is the overarching goal.
@
text
@d1 1
a1 1
# $NetBSD$
d3 2
a4 2
DISTNAME=	PyRTL-0.8.7
PKGNAME=	${PYPKGPREFIX}-${DISTNAME}
d6 1
a6 3
MASTER_SITES=	${MASTER_SITE_GITHUB:=UCSBarchlab/}
GITHUB_PROJECT=	PyRTL
GITHUB_TAG=	v${PKGVERSION_NOREV}
@