head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.4 netbsd-11-0-RC3:1.1.1.4 netbsd-11-0-RC2:1.1.1.4 binutils-2-46:1.1.1.5 netbsd-11-0-RC1:1.1.1.4 binutils-2-45:1.1.1.5 perseant-exfatfs-base-20250801:1.1.1.4 netbsd-11:1.1.1.4.0.2 netbsd-11-base:1.1.1.4 netbsd-10-1-RELEASE:1.1.1.2 perseant-exfatfs-base-20240630:1.1.1.4 binutils-2-42:1.1.1.4 perseant-exfatfs:1.1.1.3.0.2 perseant-exfatfs-base:1.1.1.3 netbsd-8-3-RELEASE:1.1.1.1 netbsd-9-4-RELEASE:1.1.1.2 netbsd-10-0-RELEASE:1.1.1.2 netbsd-10-0-RC6:1.1.1.2 netbsd-10-0-RC5:1.1.1.2 netbsd-10-0-RC4:1.1.1.2 netbsd-10-0-RC3:1.1.1.2 netbsd-10-0-RC2:1.1.1.2 netbsd-10-0-RC1:1.1.1.2 binutils-2-39:1.1.1.3 netbsd-10:1.1.1.2.0.12 netbsd-10-base:1.1.1.2 netbsd-9-3-RELEASE:1.1.1.2 cjep_sun2x-base1:1.1.1.2 cjep_sun2x:1.1.1.2.0.10 cjep_sun2x-base:1.1.1.2 cjep_staticlib_x-base1:1.1.1.2 netbsd-9-2-RELEASE:1.1.1.2 cjep_staticlib_x:1.1.1.2.0.8 cjep_staticlib_x-base:1.1.1.2 netbsd-9-1-RELEASE:1.1.1.2 phil-wifi-20200421:1.1.1.2 phil-wifi-20200411:1.1.1.2 is-mlppp:1.1.1.2.0.6 is-mlppp-base:1.1.1.2 phil-wifi-20200406:1.1.1.2 binutils-2-34:1.1.1.2 netbsd-8-2-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.2 netbsd-9-0-RC2:1.1.1.2 netbsd-9-0-RC1:1.1.1.2 phil-wifi-20191119:1.1.1.2 netbsd-9:1.1.1.2.0.4 netbsd-9-base:1.1.1.2 phil-wifi-20190609:1.1.1.2 netbsd-8-1-RELEASE:1.1.1.1 netbsd-8-1-RC1:1.1.1.1 pgoyette-compat-merge-20190127:1.1.1.1.28.1 pgoyette-compat-20190127:1.1.1.2 pgoyette-compat-20190118:1.1.1.2 pgoyette-compat-1226:1.1.1.2 pgoyette-compat-1126:1.1.1.2 binutils-2-31-1:1.1.1.2 pgoyette-compat-1020:1.1.1.2 pgoyette-compat-0930:1.1.1.2 pgoyette-compat-0906:1.1.1.2 netbsd-7-2-RELEASE:1.1.1.1 pgoyette-compat-0728:1.1.1.2 netbsd-8-0-RELEASE:1.1.1.1 phil-wifi:1.1.1.2.0.2 phil-wifi-base:1.1.1.2 pgoyette-compat-0625:1.1.1.2 netbsd-8-0-RC2:1.1.1.1 pgoyette-compat-0521:1.1.1.2 pgoyette-compat-0502:1.1.1.2 pgoyette-compat-0422:1.1.1.2 netbsd-8-0-RC1:1.1.1.1 pgoyette-compat-0415:1.1.1.2 binutils-2-30:1.1.1.2 pgoyette-compat-0407:1.1.1.1 pgoyette-compat-0330:1.1.1.1 pgoyette-compat-0322:1.1.1.1 pgoyette-compat-0315:1.1.1.1 netbsd-7-1-2-RELEASE:1.1.1.1 pgoyette-compat:1.1.1.1.0.28 pgoyette-compat-base:1.1.1.1 netbsd-7-1-1-RELEASE:1.1.1.1 matt-nb8-mediatek:1.1.1.1.0.26 matt-nb8-mediatek-base:1.1.1.1 perseant-stdc-iso10646:1.1.1.1.0.24 perseant-stdc-iso10646-base:1.1.1.1 netbsd-8:1.1.1.1.0.22 netbsd-8-base:1.1.1.1 prg-localcount2-base3:1.1.1.1 prg-localcount2-base2:1.1.1.1 prg-localcount2-base1:1.1.1.1 prg-localcount2:1.1.1.1.0.20 prg-localcount2-base:1.1.1.1 pgoyette-localcount-20170426:1.1.1.1 bouyer-socketcan-base1:1.1.1.1 pgoyette-localcount-20170320:1.1.1.1 netbsd-7-1:1.1.1.1.0.18 netbsd-7-1-RELEASE:1.1.1.1 netbsd-7-1-RC2:1.1.1.1 netbsd-7-nhusb-base-20170116:1.1.1.1 bouyer-socketcan:1.1.1.1.0.16 bouyer-socketcan-base:1.1.1.1 pgoyette-localcount-20170107:1.1.1.1 netbsd-7-1-RC1:1.1.1.1 pgoyette-localcount-20161104:1.1.1.1 binutils-2-27:1.1.1.1 netbsd-7-0-2-RELEASE:1.1.1.1 localcount-20160914:1.1.1.1 netbsd-7-nhusb:1.1.1.1.0.14 netbsd-7-nhusb-base:1.1.1.1 pgoyette-localcount-20160806:1.1.1.1 binutils-2-26-1:1.1.1.1 pgoyette-localcount-20160726:1.1.1.1 pgoyette-localcount:1.1.1.1.0.12 pgoyette-localcount-base:1.1.1.1 netbsd-7-0-1-RELEASE:1.1.1.1 binutils-2-26:1.1.1.1 netbsd-7-0:1.1.1.1.0.10 netbsd-7-0-RELEASE:1.1.1.1 netbsd-7-0-RC3:1.1.1.1 netbsd-7-0-RC2:1.1.1.1 netbsd-7-0-RC1:1.1.1.1 tls-maxphys-base:1.1.1.1 tls-maxphys:1.1.1.1.0.8 netbsd-7:1.1.1.1.0.6 netbsd-7-base:1.1.1.1 yamt-pagecache:1.1.1.1.0.4 yamt-pagecache-base9:1.1.1.1 tls-earlyentropy:1.1.1.1.0.2 tls-earlyentropy-base:1.1.1.1 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.1 riastradh-drm2-base3:1.1.1.1 binutils-2-23-2:1.1.1.1 FSF:1.1.1; locks; strict; comment @# @; 1.1 date 2013.09.29.13.40.53; author christos; state Exp; branches 1.1.1.1; next ; commitid TyuuzSx830x3Yk7x; 1.1.1.1 date 2013.09.29.13.40.53; author christos; state Exp; branches 1.1.1.1.4.1 1.1.1.1.8.1 1.1.1.1.28.1; next 1.1.1.2; commitid TyuuzSx830x3Yk7x; 1.1.1.2 date 2018.04.14.22.18.22; author christos; state Exp; branches; next 1.1.1.3; commitid ShNerhdmcUZyxsyA; 1.1.1.3 date 2022.12.23.19.01.15; author christos; state Exp; branches 1.1.1.3.2.1; next 1.1.1.4; commitid AaAP7ITTx5JnmI6E; 1.1.1.4 date 2024.06.30.16.00.27; author christos; state Exp; branches; next 1.1.1.5; commitid Eqxmo2uubpM9w1gF; 1.1.1.5 date 2025.08.25.14.42.35; author christos; state Exp; branches; next ; commitid aUBKFf4jmEzPv78G; 1.1.1.1.4.1 date 2013.09.29.13.40.53; author yamt; state dead; branches; next 1.1.1.1.4.2; commitid LcfsdHQ4HK08ayBx; 1.1.1.1.4.2 date 2014.05.22.15.54.15; author yamt; state Exp; branches; next ; commitid LcfsdHQ4HK08ayBx; 1.1.1.1.8.1 date 2013.09.29.13.40.53; author tls; state dead; branches; next 1.1.1.1.8.2; commitid jTnpym9Qu0o4R1Nx; 1.1.1.1.8.2 date 2014.08.19.23.52.30; author tls; state Exp; branches; next ; commitid jTnpym9Qu0o4R1Nx; 1.1.1.1.28.1 date 2018.04.16.01.58.21; author pgoyette; state Exp; branches; next ; commitid qk3nktk0szmTIByA; 1.1.1.3.2.1 date 2024.07.01.01.00.02; author perseant; state Exp; branches; next ; commitid NkoYLLCQWWw9v4gF; desc @@ 1.1 log @Initial revision @ text @/* MeP opcode support. -*- C -*- Copyright 2011 Free Software Foundation, Inc. Contributed by Red Hat Inc; This file is part of the GNU Binutils. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* -- opc.h */ #undef CGEN_DIS_HASH_SIZE #define CGEN_DIS_HASH_SIZE 1 #undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, insn) 0 #define CGEN_VERBOSE_ASSEMBLER_ERRORS typedef struct { char * name; int config_enum; unsigned cpu_flag; int big_endian; int vliw_bits; CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; CGEN_ATTR_VALUE_BITSET_TYPE core_isa; unsigned int option_mask; } mep_config_map_struct; extern mep_config_map_struct mep_config_map[]; extern int mep_config_index; extern void init_mep_all_core_isas_mask (void); extern void init_mep_all_cop_isas_mask (void); extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); #define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) #define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) #define MEP_OMASK (mep_config_map[mep_config_index].option_mask) #define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) #define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) #define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) #define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) #define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) #define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) #define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) #define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) #define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) /* begin-cop-ip-supported-defines */ #define MEP_IVC2_SUPPORTED 1 /* end-cop-ip-supported-defines */ extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); /* A mask for all ISAs executed by the core. */ #define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; #define MEP_INSN_CORE_P(insn) ( \ init_mep_all_core_isas_mask (), \ mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ ) /* A mask for all ISAs executed by a VLIW coprocessor. */ #define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; #define MEP_INSN_COP_P(insn) ( \ init_mep_all_cop_isas_mask (), \ mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ ) extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *); /* -- asm.c */ #include "elf/mep.h" #define CGEN_VALIDATE_INSN_SUPPORTED #define mep_cgen_insn_supported mep_cgen_insn_supported_asm const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_spreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_mep_align (CGEN_CPU_DESC, const char **, enum cgen_operand_type, long *); const char * parse_mep_alignu (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); static const char * parse_signed16 (CGEN_CPU_DESC, const char **, int, long *); static const char * parse_signed16_range (CGEN_CPU_DESC, const char **, int, long *) ATTRIBUTE_UNUSED; static const char * parse_unsigned16 (CGEN_CPU_DESC, const char **, int, unsigned long *); static const char * parse_unsigned16_range (CGEN_CPU_DESC, const char **, int, unsigned long *) ATTRIBUTE_UNUSED; static const char * parse_lo16 (CGEN_CPU_DESC, const char **, int, long *, long); static const char * parse_unsigned7 (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); static const char * parse_zero (CGEN_CPU_DESC, const char **, int, long *); const char * parse_csrn (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; unsigned long value; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (!err) return NULL; err = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, & value); if (err) return err; *field = value; return NULL; } /* begin-cop-ip-parse-handlers */ static const char * parse_ivc2_cr (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *) ATTRIBUTE_UNUSED; static const char * parse_ivc2_cr (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long *field) { return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field); } static const char * parse_ivc2_ccr (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *) ATTRIBUTE_UNUSED; static const char * parse_ivc2_ccr (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long *field) { return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field); } /* end-cop-ip-parse-handlers */ const char * parse_tpreg (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (err) return err; if (*field != 13) return _("Only $tp or $13 allowed for this opcode"); return NULL; } const char * parse_spreg (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (err) return err; if (*field != 15) return _("Only $sp or $15 allowed for this opcode"); return NULL; } const char * parse_mep_align (CGEN_CPU_DESC cd, const char ** strp, enum cgen_operand_type type, long *field) { long lsbs = 0; const char *err; switch (type) { case MEP_OPERAND_PCREL8A2: case MEP_OPERAND_PCREL12A2: case MEP_OPERAND_PCREL17A2: case MEP_OPERAND_PCREL24A2: err = cgen_parse_signed_integer (cd, strp, type, field); break; case MEP_OPERAND_PCABS24A2: case MEP_OPERAND_UDISP7: case MEP_OPERAND_UDISP7A2: case MEP_OPERAND_UDISP7A4: case MEP_OPERAND_UIMM7A4: case MEP_OPERAND_ADDR24A4: err = cgen_parse_unsigned_integer (cd, strp, type, (unsigned long *) field); break; default: abort(); } if (err) return err; switch (type) { case MEP_OPERAND_UDISP7: lsbs = 0; break; case MEP_OPERAND_PCREL8A2: case MEP_OPERAND_PCREL12A2: case MEP_OPERAND_PCREL17A2: case MEP_OPERAND_PCREL24A2: case MEP_OPERAND_PCABS24A2: case MEP_OPERAND_UDISP7A2: lsbs = *field & 1; break; case MEP_OPERAND_UDISP7A4: case MEP_OPERAND_UIMM7A4: case MEP_OPERAND_ADDR24A4: lsbs = *field & 3; break; lsbs = *field & 7; break; default: /* Safe assumption? */ abort (); } if (lsbs) return "Value is not aligned enough"; return NULL; } const char * parse_mep_alignu (CGEN_CPU_DESC cd, const char ** strp, enum cgen_operand_type type, unsigned long *field) { return parse_mep_align (cd, strp, type, (long *) field); } /* Handle %lo(), %tpoff(), %sdaoff(), %hi(), and other signed constants in a signed context. */ static const char * parse_signed16 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { return parse_lo16 (cd, strp, opindex, valuep, 1); } static const char * parse_lo16 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep, long signedp) { const char *errmsg; enum cgen_parse_operand_result result_type; bfd_vma value; if (strncasecmp (*strp, "%lo(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value &= 0xffff; if (signedp) *valuep = (long)(short) value; else *valuep = value; return errmsg; } if (strncasecmp (*strp, "%hi(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value = (value + 0x8000) >> 16; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%uhi(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value = value >> 16; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%sdaoff(", 8) == 0) { *strp += 8; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, NULL, & value); if (**strp != ')') return _("missing `)'"); ++*strp; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%tpoff(", 7) == 0) { *strp += 7; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, NULL, & value); if (**strp != ')') return _("missing `)'"); ++*strp; *valuep = value; return errmsg; } if (**strp == '%') return _("invalid %function() here"); return cgen_parse_signed_integer (cd, strp, opindex, valuep); } static const char * parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp, int opindex, unsigned long *valuep) { return parse_lo16 (cd, strp, opindex, (long *) valuep, 0); } static const char * parse_signed16_range (CGEN_CPU_DESC cd, const char **strp, int opindex, signed long *valuep) { const char *errmsg = 0; signed long value; errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (value < -32768 || value > 32767) return _("Immediate is out of range -32768 to 32767"); *valuep = value; return 0; } static const char * parse_unsigned16_range (CGEN_CPU_DESC cd, const char **strp, int opindex, unsigned long *valuep) { const char *errmsg = 0; unsigned long value; errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (value > 65535) return _("Immediate is out of range 0 to 65535"); *valuep = value; return 0; } /* A special case of parse_signed16 which accepts only the value zero. */ static const char * parse_zero (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; bfd_vma value; /*fprintf(stderr, "dj: signed parse opindex `%s'\n", *strp);*/ /* Prevent ($ry) from being attempted as an expression on 'sw $rx,($ry)'. It will fail and cause ry to be listed as an undefined symbol in the listing. */ if (strncmp (*strp, "($", 2) == 0) return "not zero"; /* any string will do -- will never be seen. */ if (strncasecmp (*strp, "%lo(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%hi(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%uhi(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%sdaoff(", 8) == 0) { *strp += 8; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%tpoff(", 7) == 0) { *strp += 7; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (**strp == '%') return "invalid %function() here"; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_NONE, &result_type, &value); if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ return errmsg; } static const char * parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp, enum cgen_operand_type opindex, unsigned long *valuep) { const char *errmsg; bfd_vma value; /* fprintf(stderr, "dj: unsigned7 parse `%s'\n", *strp); */ if (strncasecmp (*strp, "%tpoff(", 7) == 0) { int reloc; *strp += 7; switch (opindex) { case MEP_OPERAND_UDISP7: reloc = BFD_RELOC_MEP_TPREL7; break; case MEP_OPERAND_UDISP7A2: reloc = BFD_RELOC_MEP_TPREL7A2; break; case MEP_OPERAND_UDISP7A4: reloc = BFD_RELOC_MEP_TPREL7A4; break; default: /* Safe assumption? */ abort (); } errmsg = cgen_parse_address (cd, strp, opindex, reloc, NULL, &value); if (**strp != ')') return "missing `)'"; ++*strp; *valuep = value; return errmsg; } if (**strp == '%') return _("invalid %function() here"); return parse_mep_alignu (cd, strp, opindex, valuep); } static ATTRIBUTE_UNUSED const char * parse_cdisp10 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { const char *errmsg = 0; signed long value; long have_zero = 0; int wide = 0; int alignment; switch (opindex) { case MEP_OPERAND_CDISP10A4: alignment = 2; break; case MEP_OPERAND_CDISP10A2: alignment = 1; break; case MEP_OPERAND_CDISP10: default: alignment = 0; break; } if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5) wide = 1; if (strncmp (*strp, "0x0", 3) == 0 || (**strp == '0' && *(*strp + 1) != 'x')) have_zero = 1; errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (wide) { if (value < -512 || value > 511) return _("Immediate is out of range -512 to 511"); } else { if (value < -128 || value > 127) return _("Immediate is out of range -128 to 127"); } if (value & ((1<>16) & 0xffff)" }, */ /*{ "lo", "(`1 & 0xffff)" }, */ /*{ "sdaoff", "((`1-__sdabase) & 0x7f)"}, */ /*{ "tpoff", "((`1-__tpbase) & 0x7f)"}, */ { 0,0 } }; static char * expand_string (const char *, int); static const char * mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); static char * str_append (char *dest, const char *input, int len) { char *new_dest; int oldlen; if (len == 0) return dest; /* printf("str_append: <<%s>>, <<%s>>, %d\n", dest, input, len); */ oldlen = (dest ? strlen(dest) : 0); new_dest = realloc (dest, oldlen + len + 1); memset (new_dest + oldlen, 0, len + 1); return strncat (new_dest, input, len); } static macro * lookup_macro (const char *name) { macro *m; for (m = macros; m->name; ++m) if (strncmp (m->name, name, strlen(m->name)) == 0) return m; return 0; } static char * expand_macro (arg *args, int narg, macro *mac) { char *result = 0, *rescanned_result = 0; char *e = mac->expansion; char *mark = e; int mac_arg = 0; /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ while (*e) { if (*e == '`' && (*e+1) && ((*(e + 1) - '1') <= MAXARGS) && ((*(e + 1) - '1') <= narg)) { result = str_append (result, mark, e - mark); mac_arg = (*(e + 1) - '1'); /* printf("replacing `%d with %s\n", mac_arg+1, args[mac_arg].start); */ result = str_append (result, args[mac_arg].start, args[mac_arg].len); ++e; mark = e+1; } ++e; } if (mark != e) result = str_append (result, mark, e - mark); if (result) { rescanned_result = expand_string (result, 0); free (result); return rescanned_result; } else return result; } #define IN_TEXT 0 #define IN_ARGS 1 static char * expand_string (const char *in, int first_only) { int num_expansions = 0; int depth = 0; int narg = -1; arg args[MAXARGS]; int state = IN_TEXT; const char *mark = in; macro *pmacro = NULL; char *expansion = 0; char *result = 0; while (*in) { switch (state) { case IN_TEXT: if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) { pmacro = lookup_macro (in + 1); if (pmacro) { /* printf("entering state %d at '%s'...\n", state, in); */ result = str_append (result, mark, in - mark); mark = in; in += 1 + strlen (pmacro->name); while (*in == ' ') ++in; if (*in != '(') { state = IN_TEXT; pmacro = NULL; } else { state = IN_ARGS; narg = 0; args[narg].start = in + 1; args[narg].len = 0; mark = in + 1; } } } break; case IN_ARGS: if (depth == 0) { switch (*in) { case ',': narg++; args[narg].start = (in + 1); args[narg].len = 0; break; case ')': state = IN_TEXT; /* printf("entering state %d at '%s'...\n", state, in); */ if (pmacro) { expansion = 0; expansion = expand_macro (args, narg, pmacro); num_expansions++; if (expansion) { result = str_append (result, expansion, strlen (expansion)); free (expansion); } } else { result = str_append (result, mark, in - mark); } pmacro = NULL; mark = in + 1; break; case '(': depth++; default: args[narg].len++; break; } } else { if (*in == ')') depth--; if (narg > -1) args[narg].len++; } } ++in; } if (mark != in) result = str_append (result, mark, in - mark); return result; } #undef IN_ARGS #undef IN_TEXT #undef MAXARGS /* END LIGHTWEIGHT MACRO PROCESSOR. */ const char * mep_cgen_parse_operand (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); const char * mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex, const char ** strp_in, CGEN_FIELDS * fields) { const char * errmsg = NULL; char *str = 0, *hold = 0; const char **strp = 0; /* Set up a new pointer to macro-expanded string. */ str = expand_string (*strp_in, 1); /* fprintf (stderr, " expanded <<%s>> to <<%s>>\n", *strp_in, str); */ hold = str; strp = (const char **)(&str); errmsg = mep_cgen_parse_operand (cd, opindex, strp, fields); /* Now work out the advance. */ if (strlen (str) == 0) *strp_in += strlen (*strp_in); else { if (strstr (*strp_in, str)) /* A macro-expansion was pulled off the front. */ *strp_in = strstr (*strp_in, str); else /* A non-macro-expansion was pulled off the front. */ *strp_in += (str - hold); } if (hold) free (hold); return errmsg; } #define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); /* -- dis.c */ #include "elf/mep.h" #include "elf-bfd.h" #define CGEN_VALIDATE_INSN_SUPPORTED static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); static void print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, unsigned int flags ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "$tp"); } static void print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, unsigned int flags ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "$sp"); } /* begin-cop-ip-print-handlers */ static void print_ivc2_cr (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; static void print_ivc2_cr (CGEN_CPU_DESC cd, void *dis_info, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long value, unsigned int attrs) { print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs); } static void print_ivc2_ccr (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; static void print_ivc2_ccr (CGEN_CPU_DESC cd, void *dis_info, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long value, unsigned int attrs) { print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs); } /* end-cop-ip-print-handlers */ /************************************************************\ *********************** Experimental ************************* \************************************************************/ #undef CGEN_PRINT_INSN #define CGEN_PRINT_INSN mep_print_insn static int mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, bfd_byte *buf, int corelength, int copro1length, int copro2length ATTRIBUTE_UNUSED) { int i; int status = 0; /* char insnbuf[CGEN_MAX_INSN_SIZE]; */ bfd_byte insnbuf[64]; /* If corelength > 0 then there is a core insn present. It will be at the beginning of the buffer. After printing the core insn, we need to print the + on the next line. */ if (corelength > 0) { int my_status = 0; for (i = 0; i < corelength; i++ ) insnbuf[i] = buf[i]; cd->isas = & MEP_CORE_ISA; my_status = print_insn (cd, pc, info, insnbuf, corelength); if (my_status != corelength) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = corelength; } status += my_status; /* Print the + to indicate that the following copro insn is */ /* part of a vliw group. */ if (copro1length > 0) (*info->fprintf_func) (info->stream, " + "); } /* Now all that is left to be processed is the coprocessor insns In vliw mode, there will always be one. Its positioning will be from byte corelength to byte corelength+copro1length -1. No need to check for existence. Also, the first vliw insn, will, as spec'd, always be at least as long as the core insn so we don't need to flush the buffer. */ if (copro1length > 0) { int my_status = 0; for (i = corelength; i < corelength + copro1length; i++ ) insnbuf[i - corelength] = buf[i]; switch (copro1length) { case 0: break; case 2: cd->isas = & MEP_COP16_ISA; break; case 4: cd->isas = & MEP_COP32_ISA; break; case 6: cd->isas = & MEP_COP48_ISA; break; case 8: cd->isas = & MEP_COP64_ISA; break; default: /* Shouldn't be anything but 16,32,48,64. */ break; } my_status = print_insn (cd, pc, info, insnbuf, copro1length); if (my_status != copro1length) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = copro1length; } status += my_status; } #if 0 /* Now we need to process the second copro insn if it exists. We have no guarantee that the second copro insn will be longer than the first, so we have to flush the buffer if we are have a second copro insn to process. If present, this insn will be in the position from byte corelength+copro1length to byte corelength+copro1length+copro2length-1 (which better equal 8 or else we're in big trouble. */ if (copro2length > 0) { int my_status = 0; for (i = 0; i < 64 ; i++) insnbuf[i] = 0; for (i = corelength + copro1length; i < 64; i++) insnbuf[i - (corelength + copro1length)] = buf[i]; switch (copro2length) { case 2: cd->isas = 1 << ISA_EXT_COP1_16; break; case 4: cd->isas = 1 << ISA_EXT_COP1_32; break; case 6: cd->isas = 1 << ISA_EXT_COP1_48; break; case 8: cd->isas = 1 << ISA_EXT_COP1_64; break; default: /* Shouldn't be anything but 16,32,48,64. */ break; } my_status = print_insn (cd, pc, info, insnbuf, copro2length); if (my_status != copro2length) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = copro2length; } status += my_status; } #endif /* Status should now be the number of bytes that were printed which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */ if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8))) return -1; else return status; } /* The two functions mep_examine_vliw[32,64]_insns are used find out which vliw combinaion (16 bit core with 48 bit copro, 32 bit core with 32 bit copro, etc.) is present. Later on, when internally parallel coprocessors are handled, only these functions should need to be changed. At this time only the following combinations are supported: VLIW32 Mode: 16 bit core insn (core) and 16 bit coprocessor insn (cop1) 32 bit core insn (core) 32 bit coprocessor insn (cop1) Note: As of this time, I do not believe we have enough information to distinguish a 32 bit core insn from a 32 bit cop insn. Also, no 16 bit coprocessor insns have been specified. VLIW64 Mode: 16 bit core insn (core) and 48 bit coprocessor insn (cop1) 32 bit core insn (core) and 32 bit coprocessor insn (cop1) 64 bit coprocessor insn (cop1) The framework for an internally parallel coprocessor is also present (2nd coprocessor insn is cop2), but at this time it is not used. This only appears to be valid in VLIW64 mode. */ static int mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int buflength; int corebuflength; int cop1buflength; int cop2buflength; bfd_byte buf[CGEN_MAX_INSN_SIZE]; char indicator16[1]; char indicatorcop32[2]; /* At this time we're not supporting internally parallel coprocessors, so cop2buflength will always be 0. */ cop2buflength = 0; /* Read in 32 bits. */ buflength = 4; /* VLIW insn spans 4 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } /* Put the big endian representation of the bytes to be examined in the temporary buffers for examination. */ if (info->endian == BFD_ENDIAN_BIG) { indicator16[0] = buf[0]; indicatorcop32[0] = buf[0]; indicatorcop32[1] = buf[1]; } else { indicator16[0] = buf[1]; indicatorcop32[0] = buf[1]; indicatorcop32[1] = buf[0]; } /* If the two high order bits are 00, 01 or 10, we have a 16 bit core insn and a 48 bit copro insn. */ if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) { if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) { /* We have a 32 bit copro insn. */ corebuflength = 0; /* All 4 4ytes are one copro insn. */ cop1buflength = 4; } else { /* We have a 32 bit core. */ corebuflength = 4; cop1buflength = 0; } } else { /* We have a 16 bit core insn and a 16 bit copro insn. */ corebuflength = 2; cop1buflength = 2; } /* Now we have the distrubution set. Print them out. */ status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, cop1buflength, cop2buflength); return status; } static int mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int buflength; int corebuflength; int cop1buflength; int cop2buflength; bfd_byte buf[CGEN_MAX_INSN_SIZE]; char indicator16[1]; char indicator64[4]; /* At this time we're not supporting internally parallel coprocessors, so cop2buflength will always be 0. */ cop2buflength = 0; /* Read in 64 bits. */ buflength = 8; /* VLIW insn spans 8 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } /* We have all 64 bits in the buffer now. We have to figure out what combination of instruction sizes are present. The two high order bits will indicate whether or not we have a 16 bit core insn or not. If not, then we have to look at the 7,8th bytes to tell whether we have 64 bit copro insn or a 32 bit core insn with a 32 bit copro insn. Endianness will make a difference here. */ /* Put the big endian representation of the bytes to be examined in the temporary buffers for examination. */ /* indicator16[0] = buf[0]; */ if (info->endian == BFD_ENDIAN_BIG) { indicator16[0] = buf[0]; indicator64[0] = buf[0]; indicator64[1] = buf[1]; indicator64[2] = buf[2]; indicator64[3] = buf[3]; } else { indicator16[0] = buf[1]; indicator64[0] = buf[1]; indicator64[1] = buf[0]; indicator64[2] = buf[3]; indicator64[3] = buf[2]; } /* If the two high order bits are 00, 01 or 10, we have a 16 bit core insn and a 48 bit copro insn. */ if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) { if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) { /* We have a 64 bit copro insn. */ corebuflength = 0; /* All 8 bytes are one copro insn. */ cop1buflength = 8; } else { /* We have a 32 bit core insn and a 32 bit copro insn. */ corebuflength = 4; cop1buflength = 4; } } else { /* We have a 16 bit core insn and a 48 bit copro insn. */ corebuflength = 2; cop1buflength = 6; } /* Now we have the distrubution set. Print them out. */ status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, cop1buflength, cop2buflength); return status; } #ifdef MEP_IVC2_SUPPORTED static int print_slot_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, SLOTS_ATTR slot, bfd_byte *buf) { const CGEN_INSN_LIST *insn_list; CGEN_INSN_INT insn_value; CGEN_EXTRACT_INFO ex_info; insn_value = cgen_get_insn_value (cd, buf, 32); /* Fill in ex_info fields like read_insn would. Don't actually call read_insn, since the incoming buffer is already read (and possibly modified a la m32r). */ ex_info.valid = (1 << 8) - 1; ex_info.dis_info = info; ex_info.insn_bytes = buf; /* The instructions are stored in hash lists. Pick the first one and keep trying until we find the right one. */ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); while (insn_list != NULL) { const CGEN_INSN *insn = insn_list->insn; CGEN_FIELDS fields; int length; if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) { insn_list = CGEN_DIS_NEXT_INSN (insn_list); continue; } if ((insn_value & CGEN_INSN_BASE_MASK (insn)) == CGEN_INSN_BASE_VALUE (insn)) { /* Printing is handled in two passes. The first pass parses the machine insn and extracts the fields. The second pass prints them. */ length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value, &fields, pc); /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); /* Length is in bits, result is in bytes. */ return length / 8; } } insn_list = CGEN_DIS_NEXT_INSN (insn_list); } if (slot == SLOTS_P0S) (*info->fprintf_func) (info->stream, "*unknown-p0s*"); else if (slot == SLOTS_P0) (*info->fprintf_func) (info->stream, "*unknown-p0*"); else if (slot == SLOTS_P1) (*info->fprintf_func) (info->stream, "*unknown-p1*"); else if (slot == SLOTS_C3) (*info->fprintf_func) (info->stream, "*unknown-c3*"); return 0; } static int mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED) { int status; int buflength; bfd_byte buf[8]; bfd_byte insn[8]; int e; /* Read in 64 bits. */ buflength = 8; /* VLIW insn spans 8 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } if (info->endian == BFD_ENDIAN_LITTLE) e = 1; else e = 0; if (((unsigned char)buf[0^e] & 0xf0) < 0xc0) { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V1 [-----core-----][--------p0s-------][------------p1------------] */ print_insn (cd, pc, info, buf, 2); insn[0^e] = 0; insn[1^e] = buf[2^e]; insn[2^e] = buf[3^e]; insn[3^e] = buf[4^e] & 0xf0; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P0S, insn); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07) { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */ /* 00000000111111112222222233333333 */ insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4; insn[1^e] = buf[2^e]; insn[2^e] = buf[3^e]; insn[3^e] = buf[4^e] & 0xf0; print_slot_insn (cd, pc, info, SLOTS_P0, insn); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } else { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V2 [-------------core-------------]xxxx[------------p1------------] */ print_insn (cd, pc, info, buf, 4); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } return 8; } #endif /* MEP_IVC2_SUPPORTED */ /* This is a hack. SID calls this to update the disassembler as the CPU changes modes. */ static int mep_ivc2_disassemble_p = 0; static int mep_ivc2_vliw_disassemble_p = 0; void mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx); void mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx) { mep_ivc2_disassemble_p = ivc2_p; mep_ivc2_vliw_disassemble_p = vliw_p; mep_config_index = cfg_idx; } static int mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int cop_type; int ivc2 = 0; static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL; if (ivc2_core_isa == NULL) { /* IVC2 has some core-only coprocessor instructions. We use COP32 to flag those, and COP64 for the VLIW ones, since they have the same names. */ ivc2_core_isa = cgen_bitset_create (MAX_ISAS); } /* Extract and adapt to configuration number, if available. */ if (info->section && info->section->owner) { bfd *abfd = info->section->owner; mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; if (cop_type == EF_MEP_COP_IVC2) ivc2 = 1; } /* Picking the right ISA bitmask for the current context is tricky. */ if (info->section) { if (info->section->flags & SEC_MEP_VLIW) { #ifdef MEP_IVC2_SUPPORTED if (ivc2) { /* ivc2 has its own way of selecting its functions. */ cd->isas = & MEP_CORE_ISA; status = mep_examine_ivc2_insns (cd, pc, info); } else #endif /* Are we in 32 or 64 bit vliw mode? */ if (MEP_VLIW64) status = mep_examine_vliw64_insns (cd, pc, info); else status = mep_examine_vliw32_insns (cd, pc, info); /* Both the above branches set their own isa bitmasks. */ } else { if (ivc2) { cgen_bitset_clear (ivc2_core_isa); cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa); cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa); cd->isas = ivc2_core_isa; } else cd->isas = & MEP_CORE_ISA; status = default_print_insn (cd, pc, info); } } else /* sid or gdb */ { #ifdef MEP_IVC2_SUPPORTED if (mep_ivc2_disassemble_p) { if (mep_ivc2_vliw_disassemble_p) { cd->isas = & MEP_CORE_ISA; status = mep_examine_ivc2_insns (cd, pc, info); return status; } else { if (ivc2) cd->isas = ivc2_core_isa; } } #endif status = default_print_insn (cd, pc, info); } return status; } /* -- opc.c */ #include "elf/mep.h" /* A mask for all ISAs executed by the core. */ CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask = {0, 0}; void init_mep_all_core_isas_mask (void) { if (mep_all_core_isas_mask.length != 0) return; cgen_bitset_init (& mep_all_core_isas_mask, ISA_MAX); cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP); /* begin-all-core-isas */ cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1); /* end-all-core-isas */ } CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask = {0, 0}; void init_mep_all_cop_isas_mask (void) { if (mep_all_cop_isas_mask.length != 0) return; cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX); /* begin-all-cop-isas */ cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_16); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_32); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_48); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_64); /* end-all-cop-isas */ } int mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *isa_mask) { CGEN_BITSET insn_isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); return cgen_bitset_intersect_p (& insn_isas, isa_mask); } #define OPTION_MASK \ ( (1 << CGEN_INSN_OPTIONAL_BIT_INSN) \ | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN) \ | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) \ | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) \ | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) \ | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) \ | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) ) mep_config_map_struct mep_config_map[] = { /* config-map-start */ /* Default entry: first module, with all options enabled. */ { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, 0 | (1 << CGEN_INSN_OPTIONAL_CP_INSN) | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) | (1 << CGEN_INSN_OPTIONAL_BIT_INSN) | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) }, /* config-map-end */ { 0, 0, 0, 0, 0, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, 0 } }; int mep_config_index = 0; static int check_configured_mach (int machs) { /* All base insns are supported. */ int mach = 1 << MACH_BASE; switch (MEP_CPU & EF_MEP_CPU_MASK) { case EF_MEP_CPU_C2: case EF_MEP_CPU_C3: mach |= (1 << MACH_MEP); break; case EF_MEP_CPU_H1: mach |= (1 << MACH_H1); break; case EF_MEP_CPU_C5: mach |= (1 << MACH_MEP); mach |= (1 << MACH_C5); break; default: break; } return machs & mach; } int mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int iconfig = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG); int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); int ok1; int ok2; int ok3; /* If the insn has an option bit set that we don't want, reject it. */ if (CGEN_INSN_ATTRS (insn)->bool_ & OPTION_MASK & ~MEP_OMASK) return 0; /* If attributes are absent, assume no restriction. */ if (machs == 0) machs = ~0; ok1 = ((machs & cd->machs) && cgen_bitset_intersect_p (& isas, cd->isas)); /* If the insn is config-specific, make sure it matches. */ ok2 = (iconfig == 0 || iconfig == MEP_CONFIG); /* Make sure the insn is supported by the configured mach */ ok3 = check_configured_mach (machs); return (ok1 && ok2 && ok3); } int mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { #ifdef MEP_IVC2_SUPPORTED /* If we're assembling VLIW packets, ignore the 12-bit BSR as we can't relax that. The 24-bit BSR is matched instead. */ if (insn->base->num == MEP_INSN_BSR12 && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64)) return 0; #endif return mep_cgen_insn_supported (cd, insn); } @ 1.1.1.1 log @from ftp.gnu.org @ text @@ 1.1.1.1.28.1 log @Sync with HEAD, resolve some conflicts @ text @a792 1 /* Fall through. */ @ 1.1.1.2 log @2018-01-10 Nick Clifton * config-ml.in: Sync with gcc sources. * config.guess: Likewise. * config.sub: Likewise. * configure.ac: Likewise. * configure: Regenerate. 2017-12-14 Nick Clifton * COPYING.LIBGLOSS: Update address of FSF in copyright notice. 2017-12-12 Stafford Horne * configure.ac: Remove logic adding gdb to noconfigsdirs for or1k. * configure: Regenerate. 2017-09-15 Nick Clifton * src-release.sh (LZIPPROG): New define. Provides the name of the lzip program. (do_lz): New function. Compresses a tarball using the lzip program. (do_compress): Add support for lzip compression. (usage): Mention -l option. (build_release): Support -l option to invoke lzip compression. 2017-09-15 Alan Modra * src-release.sh (do_proto_toplev): Revert last patch. Enable or disable binutils, gas, gdb, gold, gprof, ld, libdecnumber, readline, and sim depending on $tool and $support_files. Echo configure line. 2017-09-14 Matt Rice * src-release.sh (do_proto_toplev): Enable gold during release process. 2017-04-13 Andrew Jenner * config.sub: Sync with master version in config project. 2017-04-03 Andrew Jenner * config.sub: Handle ia16 in $basic_machine. bfd/ * config.bfd: Handle ia16. gas/ * configure.tgt: Handle ia16. ld/ * configure.tgt: Handle ia16. 2017-03-22 Nick Clifton * config.sub: Sync with master version in config project. * config.guess: Likewise. 2017-01-23 Nick Clifton * configure.ac: Update year in copyright notice. Sync from FSF GCC mainline, bringing in the following patches. * Makefile.def: Likewise. * Makefile.tpl: Likewise. * configure: Regenerate. * Makefile.in: Regenerate. 2016-12-21 Jakub Jelinek * configure.ac: Don't bootstrap libmpx unless --with-build-config includes bootstrap-mpx. 2016-12-01 Matthias Klose * configure.ac: Don't use pkg-config to check for bdw-gc. 2016-11-30 Matthias Klose * Makefile.def: Remove reference to boehm-gc target module. * configure.ac: Include pkg.m4, check for --with-target-bdw-gc options and for the bdw-gc pkg-config module. 2016-11-15 Matthias Klose * config-ml.in: Remove references to GCJ. * configure.ac: Likewise. 2016-09-30 Jakub Jelinek * configure.ac: Add target-libffi to target_libraries. Readd libgcj target disablings, modified to only target-libffi. Readd target addition of go to unsupported languages. 2016-09-30 Andrew Haley * Makefile.def: Remove libjava. * Makefile.tpl: Likewise. * configure.ac: Likewise. 2016-09-26 Anton Kolesov * configure.ac: Disable "sim" directory for arc*-*-*. 2016-09-12 Maciej W. Rozycki * configure.ac: Check for the minimum in-tree MPFR version handled. 2016-12-31 Alan Modra * config.sub: Import from upstream. 2016-12-08 Alan Modra * configure: Regenerate. 2016-12-02 Josh Conner * configure.ac: Add fuchsia to targets that use ELF. * configure: Regenerated. 2016-11-07 Doug Evans * config.sub: Sync with upstream version 2016-11-03. git://git.sv.gnu.org/config.git * config.guess: Sync with upstream version 2016-10-02. 2016-09-27 Simon Marchi * .gitignore: Add archives and make stamps. 2016-07-20 Yan-Ting Lin * configure.ac (nds32*-*-*): Remove entry to enable gdb. * configure: Regenerated. @ text @a792 1 /* Fall through. */ @ 1.1.1.3 log @Update binutils from 2.34 to 2.39 2022-07-08 Nick Clifton * 2.39 branch created. 2022-07-04 Nick Clifton * libiberty: Synchronize with GCC. Bring in: 2022-07-01 Nick Clifton PR demangler/105039 * rust-demangle.c (demangle_const): Add recursion limit. 2022-06-26 Simon Marchi * configure.ac: Add AC_CONFIG_MACRO_DIRS call. * configure: Re-generate. 2022-04-12 Nick Clifton * zlib: Rebase to the 1.2.12 release. 2022-04-08 Simon Marchi * configure.ac: Add AC_SUBST(PKG_CONFIG_PATH). * configure: Re-generate. * Makefile.tpl (HOST_EXPORTS): Pass PKG_CONFIG_PATH. (PKG_CONFIG_PATH): New. * Makefile.in: Re-generate. 2022-03-15 Jose E. Marchesi * gprofng/src/gp-collect-app.cc (collect::check_args): Use fallthrough comment instead of attribute. 2022-03-11 Vladimir Mezentsev * Makefile.def: Add gprofng module. * configure.ac: Add --enable-gprofng option. * src-release.sh: Add gprofng. * Makefile.in: Regenerate. * configure: Regenerate. * gprofng: New directory. 2022-01-22 Nick Clifton * 2.38 release branch created. 2022-01-17 Nick Clifton Update config.[guess|sub] from upstream: 2022-01-09 Idan Horowitz config.guess: recognize SerenityOS * config.guess (*:SerenityOS:*:*): Recognize. (timestamp): Update. 2022-01-03 Bernhard Voelker Fix GPLv3 license headers to use a comma instead of semicolon See: https://www.gnu.org/licenses/gpl-3.0.html#howto Update license headers automatically using the following script: $ git grep -l 'Foundation; either version 3' \ | xargs sed -i '/Foundation; either version 3/ s/n; e/n, e/' * config.guess: Adjust via the above command. (timestamp): Update. * config.sub: Likewise. * doc/config.guess.1: Regenerate. * doc/config.sub.1: Likewise. 2022-01-01 Dmitry V. Levin Update copyright years * config.guess: Update copyright years. * config.sub: Likewise. 2021-12-25 Dmitry V. Levin config.sub: alias armh to armv7l ALT uses armh as an alias for armv7l-alt-linux-gnueabihf since 2012. * config.sub (armh-unknown|armh-alt): Set cpu, vendor, and basic_os. (timestamp): Update. 2021-12-24 Dmitry V. Levin config.sub: alias aarch64le to aarch64 Apparently, QNX reports aarch64 as aarch64le on little-endian machines. * config.sub (aarch64le-*): Set cpu to aarch64. (timestamp): Update. 2021-12-13 Dmitry V. Levin config.sub: fix typo in timestamp * config.sub: Fix timestamp. 2021-11-30 Andreas F. Borchert config.guess: x86_64-pc-solaris2.11 is not properly recognized config.guess guesses Solaris 11 to run on a 32-bit platform despite Solaris 11 no longer supporting any 32-bit platform. See the following code at lines 434 to 445: | SUN_ARCH=i386 | # If there is a compiler, see if it is configured for 64-bit objects. | # Note that the Sun cc does not turn __LP64__ into 1 like gcc does. | # This test works for both compilers. | if test "$CC_FOR_BUILD" != no_compiler_found; then | if (echo '#ifdef __amd64'; echo IS_64BIT_ARCH; echo '#endif') | \ | (CCOPTS="" $CC_FOR_BUILD -E - 2>/dev/null) | \ | grep IS_64BIT_ARCH >/dev/null | then | SUN_ARCH=x86_64 | fi | fi If "cc" is installed, i.e. the Oracle Studio compiler, this one is chosen for $CC_FOR_BUILD. This compiler, the gcc provided by Oracle and also gcc bootstrapped from sources on that platform with a default configuration will by default generate 32-bit binaries -- even on a 64-bit platform. And __amd64 will not be defined for compilations targeting a 32-bit platform. This is different from the corresponding behaviour on GNU/Linux systems where the local platform is targeted by default. Thus, as long as you do not add "-m64" or if you have a custom-built gcc which defaults to 64 bit, you will get 32-bit binaries on Solaris despite living on a 64-bit platform. * config.guess (i86pc:SunOS:5.*:* || i86xen:SunOS:5.*:*): Adapt the test by adding the "-m64" flag. This will work properly for Solaris 10 as well (the last Solaris release that supported x86 32-bit platforms). 2021-10-27 Jordi Sanfeliu Recognize Fiwix $ make check cd testsuite && bash config-guess.sh && rm uname PASS: config.guess checks (137 tests) cd testsuite && bash config-sub.sh PASS: config.sub checks (882 tests) PASS: config.sub idempotency checks (819 tests) PASS: config.sub canonicalise each config.guess testcase (137 tests) * config.guess (i*86:Fiwix:*:*): Recognize. * config.sub (fiwix*): Likewise. 2021-10-18 Kinshuk Dua config.sub: Fix typo in comment Fixes: 5e531d391852a54e7fab2d8ff55625fca514b305 2021-08-14 Nick Bowler config.sub: work around command assignment bug in some shells When combining variable assignments with a shell command, some older shells (notably heirloom-sh and presumably also Solaris 10 /bin/sh) have a bug which causes the assignment to alter the current execution environment whenever the command is a shell built-in. For example: % dash -c 'x=good; x=bad echo >/dev/null; echo $x' good % jsh -c 'x=good; x=bad echo >/dev/null; echo $x' bad The config.sub script contains a few commands of the form: IFS=- read ... which triggers this bug, causing the IFS assignment to persist for the remainder of the script. This can cause misbehaviour in certain cases, for example: % jsh config.sub i386-linux-gnu config.sub: test: unknown operator gnu % jsh config.sub i386-gnu/linux sed: can't read s|gnu/linux|gnu|: No such file or directory Invalid configuration `i386-gnu/linux': OS `' not recognized * config.sub: Save and restore IFS explicitly to avoid shell bugs. * doc/config.sub.1: Regenerate. 2021-08-04 Jeremy Soller config.sub: add Linux Relibc Target $ make check cd testsuite && bash config-guess.sh && rm uname PASS: config.guess checks (136 tests) cd testsuite && bash config-sub.sh PASS: config.sub checks (881 tests) PASS: config.sub idempotency checks (818 tests) PASS: config.sub canonicalise each config.guess testcase (136 tests) * config.sub (relibc*): Recognize. * doc/config.sub.1: Regenerate. * testsuite/config-sub.data (x86_64-linux-relibc): New test. 2021-07-06 Stephanos Ioannidis config.sub: add Zephyr RTOS support This adds the Zephyr RTOS targets in preparation for implementing the Zephyr RTOS-specific toolchain support. $ make check cd testsuite && bash config-guess.sh && rm uname PASS: config.guess checks (136 tests) cd testsuite && bash config-sub.sh PASS: config.sub checks (880 tests) PASS: config.sub idempotency checks (817 tests) PASS: config.sub canonicalise each config.guess testcase (136 tests) * config.sub (zephyr*): Recognize. * doc/config.sub.1: Regenerate. * testsuite/config-sub.data: Add testcases for *-zephyr. 2021-07-03 Ozkan Sezer config.sub: disable shellcheck SC2006 / SC2268 warnings This is in line with the recent config.guess change in commit 12fcf67c9108f4c4b581eaa302088782f0ee40ea * config.sub (shellcheck disable): Add SC2006,SC2268. Suggested-by: Jacob Bachmeyer 2021-07-03 Ozkan Sezer config.sub: normalize the quoting in the `echo FOO | sed ...` Some cases quote the argument to echo and some do not. At runtime it probably does not matter because the substituted values will never contain whitespace, but quoting them all would make shellcheck more useful. * config.sub: Consistently quote the argument of echo. * doc/config.sub.1: Regenerate. Suggested-by: Jacob Bachmeyer 2021-07-02 Ozkan Sezer config.sub: replace POSIX $( ) with classic ` ` throughout This is in line with the recent config.guess change in commit d70c4fa934de164178054c3a60aaa0024ed07c91. The patch was generated using patch-6.gawk script introduced in that commit. * config.sub: Revert POSIX command substitutions to classic form. 2021-06-04 Vineet Gupta Recognize arc32 This is the 32-bit variant of ARCv3 ISA (which is not compatible with the 32-bit ARCv2 ISA) | make check | cd testsuite && bash config-guess.sh && rm uname | PASS: config.guess checks (136 tests) | cd testsuite && bash config-sub.sh | PASS: config.sub checks (864 tests) | PASS: config.sub idempotency checks (801 tests) | PASS: config.sub canonicalise each config.guess testcase (136 tests) * config.guess (arc32:Linux:*:*): Recognize. * config.sub (arc32): Likewise. 2021-05-27 Jacob Bachmeyer Remove automatic patch generators These tools have served their purposes and need not be kept outside of the repository history any longer. This patch as a diff also collects the contents of the various tools in one convenient place. * patch-1.gawk: Remove. * patch-3.gawk: Likewise. * patch-6.gawk: Likewise. 2021-05-26 Jacob Bachmeyer config.guess: manual fixups after previous automatic patch The tool could not handle command substitutions that span lines, but fortunately there were only two such substitutions in the script. The test for which universe is active on Pyramid is rewritten into a case block because it was the only use of a command substitution as an argument to the test command, which would require quoting. * config.guess: Rewrite "if" for Pyramid systems to "case". 2021-05-26 Jacob Bachmeyer config.guess: replace POSIX $( ) with classic ` ` throughout The previous replacement of backticks with POSIX command substitutions was ill-considered and illogical: this script recognizes many archaic machine types that probably never had POSIX shells, therefore it needs to be able to run successfully under pre-POSIX shells. This patch was generated using the included GNU Awk program. * config.guess: Revert POSIX command substitutions to classic form. * patch-6.gawk: Store the tool that produced the automated patch. 2021-05-26 Jacob Bachmeyer config.guess: manual fixup after previous automated patches This patch provides the special handling for the GNU system. As these were two small and unique edits, they were not included in the scripts. This patch also cleans up other minor issues that must be addressed before reverting to classic command substitutions and updates "shellcheck" directives to account for changes in this script and the change in "shellcheck" towards reporting individual portability issues. 2021-05-26 Jacob Bachmeyer config.guess: automatic fixups after previous automated patch This patch was generated using the following command: sed -i config.guess \ -e '/="[^"]\+"\(-\|$\)/s/="\([^"([:space:])]\+\)"/=\1/' \ -e '/="[^"]\+"[[:alnum:]]/s/="\$\([^([:space:])]\+\)"/=${\1}/' \ -e \ '/\$(echo[^|]\+|/s/\([^[:space:]]\)[[:space:]]*|[[:space:]]*sed/\1 | sed/g' * config.guess: Remove unneeded quotes in other variable assignments, standardize spacing for "echo ... | sed" substitutions. 2021-05-26 Jacob Bachmeyer config.guess: remove unneeded quotes and factor command substitutions This is further cleanup and simplifies some constructs that can confuse Emacs' syntax highlighting while generally reducing required quoting. This patch was generated using the included GNU Awk program. * config.guess: Remove unneeded variable quotes and factor out command substitutions when setting GUESS. * patch-3.gawk: Store the tool that produced the automated patch. 2021-05-25 Jacob Bachmeyer config.guess: manual fixups after previous automatic patch * config.guess: Adjust a few "leftover" cases that the tool could not easily recognize and fixes comment indentation in a few other special cases. 2021-05-25 Jacob Bachmeyer config.guess: use intermediate variable with uname results This will allow quoting to be significantly simplified in another pass through the file. This patch was generated using the included GNU Awk program. * config.guess: Use GUESS variable to hold results of uname analysis. * patch-1.gawk: Store the tool that produced the automated patch. 2021-05-25 Jacob Bachmeyer config.guess: introduce intermediate variable with uname results This will allow quoting to be significantly simplified in another pass through the file. * config.guess: Introduce GUESS variable to hold results of uname analysis. 2021-05-24 Dmitry V. Levin config.guess: fix shellcheck warning SC2154 While, according to Plan 9 documentation, the environment variable $cputype is set to the name of the kernel's CPU's architecture, shellcheck warns that cputype is referenced but not assigned. Be on the safe side and do not use cputype if it is not defined or empty. * config.guess (*:Plan9:*:*): Fix shellcheck warning SC2154. 2021-05-24 Dmitry V. Levin config.guess: remove redundant quotes in case commands According to the GNU Autoconf Portable Shell Programming manual, the Bourne shell does not systematically split variables and back-quoted expressions, in particular on the right-hand side of assignments and in the argument of 'case'. The change is made automatically using the following command: $ sed -E -i 's/(\)/\1\2\3/' config.guess * config.guess: Simplify case commands by removing quotes around the argument. Suggested-by: Jacob Bachmeyer 2021-05-24 Dmitry V. Levin config.guess: simplify exit status workaround on alphaev67-dec-osf5.1 Commit 29865ea8a5622cdd80b7a69a0afa78004b4cd311 introduced an exit trap reset before exiting to avoid a spurious non-zero exit status on alphaev67-dec-osf5.1. Simplify that code a bit by moving the exit trap reset around. * config.guess (alpha:OSF1:*:*): Reset exit trap earlier. * doc/config.guess.1: Regenerate. 2021-10-29 Eli Zaretskii * gdb/doc/gdb.texinfo (Command Options): (Data): Document '-memory-tag-violations'. Update the example. 2021-09-28 Andrew Burgess * src-release.sh (GDB_SUPPPORT_DIRS): Add libbacktrace. 2021-09-27 Nick Alcock PR libctf/27967 * libtool.m4 (LT_PATH_NM): Try BSDization flags with a user-provided NM, if there is one. Run nm on itself, not on /dev/null, to avoid errors from nms that refuse to work on non-regular files. Remove other workarounds for this problem. Strip out blank lines from the nm output. 2021-09-27 Nick Alcock PR libctf/27967 * libtool.m4 (lt_cv_sys_global_symbol_pipe): Augment symcode for Solaris 11. 2021-07-03 Nick Clifton * 2.37 release branch created. 2021-07-03 Nick Clifton * libiberty: Sync with gcc. Bring in: 2021-06-30 Gerald Pfeifer * make-temp-file.c (usrtmp): Remove. (choose_tmpdir): Remove use of usrtmp. 2021-06-28 Indu Bhagat * simple-object.c (handle_lto_debug_sections): Copy over .BTF section. 2021-06-28 Indu Bhagat David Faust Jose E. Marchesi Weimin Pan * simple-object.c (handle_lto_debug_sections): Copy over .ctf sections. 2021-06-05 John David Anglin PR target/100734 * configure.ac: Use libiberty snprintf and vsnprintf on hppa*-*-hpux*. * configure: Regenerate. 2021-05-06 Tom Tromey * hashtab.c (htab_eq_string): New function. 2021-05-04 Eric Botcazou * configure.ac: Make test for variables more robust. * configure: Regenerate. 2021-05-03 H.J. Lu PR bootstrap/99703 * configure: Regenerated. 2021-04-21 Andreas Schwab PR demangler/100177 * rust-demangle.c (demangle_const_char): Properly print the character value. 2021-03-31 Patrick Palka PR c++/88115 * cp-demangle.c (d_dump, d_make_comp, d_expression_1) (d_count_templates_scopes): Handle DEMANGLE_COMPONENT_VENDOR_EXPR. (d_print_comp_inner): Likewise. : Revert r11-4926 change. : Likewise. * testsuite/demangle-expected: Adjust __alignof__ tests. 2021-03-16 Nick Clifton * sha1.c (sha1_process_bytes): Use memmove in place of memcpy. 2021-02-20 Mike Frysinger * Makefile.in (ACLOCAL, ACLOCAL_AMFLAGS, $(srcdir)/aclocal.m4): Define. (configure_deps): Rename to ... (aclocal_deps): ... this. Replace aclocal.m4 with acinclude.m4. ($(srcdir)/configure): Replace $(configure_deps) with $(srcdir)/aclocal.m4. * aclocal.m4: Move libiberty macros to acinclude.m4, then regenerate. * acinclude.m4: New file. * configure: Regenerate. 2021-02-19 Ayush Mittal * argv.c (expandargv): free allocated buffer if read fails. 2021-02-01 Martin Sebor * dyn-string.c (dyn_string_insert_cstr): Use memcpy instead of strncpy to avoid -Wstringop-truncation. 2021-05-29 Mike Frysinger * configure.ac: Add gnulib to configdirs for sim. * configure: Regenerate. 2021-05-24 Maciej W. Rozycki * MAINTAINERS: Update path to readline config.{sub,guess} files. 2021-05-24 Maciej W. Rozycki * config.guess: Import from upstream. * config.sub: Likewise. 2021-05-18 Mike Frysinger * Makefile.def: Add configure-sim dependency on all-gnulib. * Makefile.in: Regenerated. 2021-05-04 Nick Clifton * configure.ac (AC_PROG_CC): Replace with AC_PROG_CC_C99. * configure: Regenerate. 2021-03-18 Nick Alcock PR libctf/27482 * Makefile.def: Add install-bfd dependencies for install-libctf and install-ld, and install-strip-bfd dependencies for install-strip-libctf and install-strip-ld; move the install-ld dependency on install-libctf to join it. * Makefile.in: Regenerated. 2021-03-12 Mike Frysinger * Makefile.def: Remove all-sim dependency on configure-gdb. * Makefile.in: Regenerated. 2021-02-28 H.J. Lu PR binutils/26766 * Makefile.tpl (PGO_BUILD_TRAINING_FLAGS_TO_PASS): Add PGO_BUILD_TRAINING=yes. (PGO_BUILD_TRAINING_MFLAGS): New. (all): Pass $(PGO_BUILD_TRAINING_MFLAGS) to the PGO build. 2021-02-09 Alan Modra * configure.ac: Delete arm*-*-symbianelf* entry. * configure: Regenerate. 2021-01-26 Nick Alcock * Makefile.def: Add install-libctf dependency to install-ld. * Makefile.in: Regenerated. 2021-01-12 Mike Frysinger * src-release.sh (do_proto_toplev): Rewrite indentation. 2021-01-11 H.J. Lu PR binutils/26766 * configure.ac: * configure: Regenerated. 2021-01-11 H.J. Lu PR ld/27173 * configure: Regenerated. * libtool.m4 (_LT_CMD_OLD_ARCHIVE): Check if AR works with --plugin and rc before enabling --plugin. 2021-01-09 H.J. Lu PR binutils/26766 * Makefile.tpl (BUILD_CFLAGS): New. (CFLAGS): Append $(BUILD_CFLAGS). (CXXFLAGS): Likewise. (PGO_BUILD_GEN_FLAGS_TO_PASS): New. (PGO_BUILD_TRAINING_CFLAGS): Likewise. (PGO_BUILD_TRAINING_CXXFLAGS): Likewise. (PGO_BUILD_TRAINING_FLAGS_TO_PASS): Likewise. (PGO_BUILD_TRAINING_MFLAGS): Likewise. (PGO_BUILD_USE_FLAGS_TO_PASS): Likewise. (PGO-TRAINING-TARGETS): Likewise. (PGO_BUILD_TRAINING): Likewise. (all): Add '+' to the command line for recursive make. Support the PGO build. * configure.ac: Add --enable-pgo-build[=lto]. AC_SUBST PGO_BUILD_GEN_CFLAGS, PGO_BUILD_USE_CFLAGS and PGO_BUILD_LTO_CFLAGS. Enable the PGO build in Makefile. * Makefile.in: Regenerated. * configure: Likewise. 2021-01-09 H.J. Lu * Makefile.tpl (AR): Add @@AR_PLUGIN_OPTION@@ (RANLIB): Add @@RANLIB_PLUGIN_OPTION@@. * configure.ac: Include config/gcc-plugin.m4. AC_SUBST AR_PLUGIN_OPTION and RANLIB_PLUGIN_OPTION. * libtool.m4 (_LT_CMD_OLD_ARCHIVE): Pass --plugin to AR and RANLIB if possible. * Makefile.in: Regenerated. * configure: Likewise. 2021-01-09 Nick Clifton * 2.36 release branch crated. 2021-01-07 Samuel Thibault * libtool.m4: Match gnu* along with other GNU systems. 2021-01-07 Alan Modra * config.sub: Accept OS of eabi* and gnueabi*. 2021-01-05 Nick Alcock * Makefile.def (libctf): No longer no_check. Checking depends on all-ld. * Makefile.in: Regenerated. 2021-01-05 Nick Clifton * libiberty: Sync with gcc. Bring in: 2021-01-04 Martin Liska * strverscmp.c: Convert to utf8 from iso8859. 2020-12-22 Jason Merrill PR c++/67343 * cp-demangle.h (struct d_info): Add unresolved_name_state. * cp-demangle.c (d_prefix): Add subst parm. (d_nested_name): Pass it. (d_unresolved_name): Split out from... (d_expression_1): ...here. (d_demangle_callback): Maybe retry with old sr mangling. * testsuite/demangle-expected: Add test. 2020-12-21 Jason Merrill * cp-demangle.c (d_expression_1): Recognize qualified-id on RHS of dt/pt. * testsuite/demangle-expected: Add test. 2020-12-21 Jason Merrill * cp-demangle.c (d_unqualified_name): Clear is_expression. * testsuite/demangle-expected: Add tests. 2020-11-25 Matthew Malcomson * configure: Regenerate. * configure.ac: Avoid using sanitizer. 2020-11-13 Eduard-Mihai Burtescu * rust-demangle.c (struct rust_demangler): Add skipping_printing and bound_lifetime_depth fields. (eat): Add (v0-only). (parse_integer_62): Add (v0-only). (parse_opt_integer_62): Add (v0-only). (parse_disambiguator): Add (v0-only). (struct rust_mangled_ident): Add punycode{,_len} fields. (parse_ident): Support v0 identifiers. (print_str): Respect skipping_printing. (print_uint64): Add (v0-only). (print_uint64_hex): Add (v0-only). (print_ident): Respect skipping_printing, Support v0 identifiers. (print_lifetime_from_index): Add (v0-only). (demangle_binder): Add (v0-only). (demangle_path): Add (v0-only). (demangle_generic_arg): Add (v0-only). (demangle_type): Add (v0-only). (demangle_path_maybe_open_generics): Add (v0-only). (demangle_dyn_trait): Add (v0-only). (demangle_const): Add (v0-only). (demangle_const_uint): Add (v0-only). (basic_type): Add (v0-only). (rust_demangle_callback): Support v0 symbols. * testsuite/rust-demangle-expected: Add v0 testcases. 2020-11-13 Seija Kijin * strstr.c (strstr): Make implementation ANSI/POSIX compliant. 2020-11-11 Patrick Palka PR c++/88115 * cp-demangle.c (d_print_comp_inner) : Don't print the "operator " prefix for __alignof__. : Always print parens around the operand of __alignof__. * testsuite/demangle-expected: Test demangling for __alignof__. 2020-11-09 Christophe Lyon * pex-win32.c (pex_win32_exec_child): Initialize orig_err. 2020-10-06 Martin Liska PR lto/97290 * simple-object-elf.c (simple_object_elf_copy_lto_debug_sections): Use sh_link of a .symtab_shndx section. 2021-01-05 Alan Modra * config.guess: Import from upstream. * config.sub: Likewise. 2020-12-16 Martin Liska Tom de Vries * gdb/debuginfod-support.c (struct user_data): Remove has_printed field. Add meter field. (progressfn): Print progress using meter. 2020-12-02 Enze Li * .gitignore: Add gnu global outputs. 2020-12-02 Simon Marchi * .gitignore: Sync with gcc. 2020-10-26 Andreas Rammhold * src-release.sh: Use sha256sum instead of md5sum. 2020-10-14 Andrew Burgess * Makefile.in: Rebuild. * Makefile.def: Make distclean-gnulib depend on distclean-gdb and distclean-gdbserver. 2020-07-24 Aaron Merey * configure: Rebuild. * configure.ac: Remove AC_DEBUGINFOD. 2020-07-04 Nick Clifton Binutils 2.35 branch created. 2020-04-21 Stephen Casner PR 25830 * configure.ac (noconfigdirs): Exclude gdb & gprof for pdp11. * configure: Rebuild. 2020-03-12 Tom Tromey * Makefile.in: Rebuild. * Makefile.def (gdbserver): Depend on gdbsupport. 2020-03-12 Tom Tromey * Makefile.in: Rebuild. * Makefile.def (gdbsupport): Don't depend on bfd. 2020-03-12 Tom Tromey * Makefile.in: Rebuild. * Makefile.def (gdbsupport): Depend on intl. 2020-02-17 Tom Tromey * configure: Rebuild. * configure.ac (configdirs): Add gnulib and gdbsupport when building gdbserver. 2020-02-14 Tom Tromey * Makefile.in: Rebuild. * Makefile.def: Make gdbserver require gnulib and libiberty. 2020-02-07 Tom Tromey Pedro Alves * src-release.sh (GDB_SUPPORT_DIRS): Add gdbserver. * gdbserver: New directory, moved from gdb/gdbserver. * configure.ac (host_tools): Add gdbserver. Only build gdbserver on certain systems. * Makefile.in, configure: Rebuild. * Makefile.def (host_modules, dependencies): Add gdbserver. * MAINTAINERS: Add gdbserver. 2020-01-28 Sergio Durigan Junior * src-release.sh (getver): Look for gdbsupport's create-version.sh script at the current directory if tool is "gdb". 2020-01-19 Simon Marchi * remote-sim.c (gdbsim_target::wait): Return sim_data->remote_sim_ptid instead of inferior_ptid. @ text @d629 1 a629 1 static macro const macros[] = d662 1 a662 1 static const macro * d665 1 a665 1 const macro *m; d675 1 a675 1 expand_macro (arg *args, int narg, const macro *mac) d725 1 a725 1 const macro *pmacro = NULL; d858 2 a859 1 free (hold); d873 3 d877 1 a877 1 print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void *dis_info, d887 1 a887 1 print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void *dis_info, d1275 1 a1275 1 insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian); d1455 2 a1456 4 if (bfd_get_flavour (abfd) == bfd_target_elf_flavour) { mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ d1458 3 a1460 4 cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; if (cop_type == EF_MEP_COP_IVC2) ivc2 = 1; } @ 1.1.1.3.2.1 log @Sync with HEAD. @ text @d85 1 a85 1 #define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask d536 1 a536 1 abort (); d582 1 a582 1 if (strncmp (*strp, "0x0", 3) == 0 d649 1 a649 1 { d685 4 a688 4 if (*e == '`' && (*e+1) && ((*(e + 1) - '1') <= MAXARGS) && ((*(e + 1) - '1') <= narg)) d709 1 a709 1 else d734 2 a735 2 if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) { d746 1 a746 1 state = IN_TEXT; d755 1 a755 1 mark = in + 1; d796 1 a796 1 break; d798 1 a798 1 } d806 1 d810 1 a810 1 d813 1 a813 1 d852 1 a852 1 *strp_in = strstr (*strp_in, str); d855 1 a855 1 *strp_in += (str - hold); d863 1 a863 1 #define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); d948 1 a948 1 d952 1 a952 1 d961 2 a962 2 /* Print the + to indicate that the following copro insn is part of a vliw group. */ d964 1 a964 1 (*info->fprintf_func) (info->stream, " + "); d976 1 a976 1 d995 1 a995 1 break; d1028 1 a1028 1 d1041 1 a1041 1 cd->isas = 1 << ISA_EXT_COP1_64; d1069 5 a1073 7 /* The two functions mep_examine_vliw[32,64]_insns are used find out which vliw combinaion (16 bit core with 48 bit copro, 32 bit core with 32 bit copro, etc.) is present. Later on, when internally parallel coprocessors are handled, only these functions should need to be changed. At this time only the following combinations are supported: d1075 2 d1083 1 a1083 1 no 16 bit coprocessor insns have been specified. d1089 1 a1089 1 d1091 1 a1091 1 present (2nd coprocessor insn is cop2), but at this time it d1102 1 a1102 1 bfd_byte buf[CGEN_MAX_INSN_SIZE]; d1104 1 a1104 1 char indicatorcop32[2]; d1143 2 a1144 2 /* We have a 32 bit copro insn. */ corebuflength = 0; d1146 1 a1146 1 cop1buflength = 4; d1150 3 a1152 3 /* We have a 32 bit core. */ corebuflength = 4; cop1buflength = 0; d1232 2 a1233 2 /* We have a 64 bit copro insn. */ corebuflength = 0; d1235 1 a1235 1 cop1buflength = 8; d1239 3 a1241 3 /* We have a 32 bit core insn and a 32 bit copro insn. */ corebuflength = 4; cop1buflength = 4; d1293 2 a1294 2 { insn_list = CGEN_DIS_NEXT_INSN (insn_list); d1296 1 a1296 1 } a1455 14 /* mep_config_map is a variable sized array, so we do not know how big it is. The only safe way to check the index therefore is to iterate over the array. We do know that the last entry is all null. */ int i; for (i = 0; i <= mep_config_index; i++) if (mep_config_map[i].name == NULL) break; if (i < mep_config_index) { opcodes_error_handler (_("illegal MEP INDEX setting '%x' in ELF header e_flags field"), mep_config_index); mep_config_index = 0; } @ 1.1.1.4 log @Import binutils-2.42 (last was 2.39) 2024-01-15 Nick Clifton * 2.42 branch point. 2023-11-15 Arsen Arsenović * intl: Remove directory. Replaced with out-of-tree GNU gettext. * .gitignore: Add '/gettext*'. * configure.ac (host_libs): Replace intl with gettext. (hbaseargs, bbaseargs, baseargs): Split baseargs into {h,b}baseargs. (skip_barg): New flag. Skips appending current flag to bbaseargs. : Exempt --with-libintl-{type,prefix} from target and build machine argument passing. * configure: Regenerate. * Makefile.def (host_modules): Replace intl module with gettext module. (configure-ld): Depend on configure-gettext. * Makefile.in: Regenerate. * src-release.sh: Remove references to the intl/ directory. 2023-07-03 Nick Clifton 2.41 Branch Point. 2023-06-26 Nick Clifton * Import these updates to the config scripts commit 4ad4bb7c30aca1e705448ba8d51a210bbd47bb52 Author: Paul Eggert Date: Fri Jun 23 09:55:10 2023 -0700 Quote 'like this', not `like this'. commit 63acb96f92473ceb5e21d873d7c0aee266b3d6d3 Author: Paul Eggert Date: Sat Jan 21 00:15:01 2023 -0600 Fix config.sub spelling typo for "athlon" commit 4ce12a5c9125cedc0d0ba584444a6865396923ec Author: Dmitry V. Levin Date: Sun Jan 1 08:00:00 2023 +0000 Update copyright years commit c397e2c040bce50bcdccb131f90115ba7e8bfc19 Author: Arsen Arsenovi Date: Sat Sep 17 23:34:48 2022 +0200 config.sub: add linux-mlibc targets commit 9f9f9b0b13197269848c76e3e057a3ed0680b4bf Author: Arsen Arsenovi Date: Sat Sep 17 23:34:47 2022 +0200 config.guess: support running on Managarm systems commit 87e6687749da7bb2ab158a79fa83721c19ed9246 Author: Arsen Arsenovi Date: Sat Sep 17 23:34:46 2022 +0200 config.sub: add managarm-{mlibc,kernel} targets commit 20403c5701973a4cbd7e0b4bbeb627fcd424a0f1 Author: Xiaotian Wu Date: Mon Aug 1 16:05:29 2022 +0800 Remove loongarchx32 commit 02ba26b218d3d3db6c56e014655faf463cefa983 Author: Alexander von Gluck IV Date: Wed May 25 15:43:13 2022 -0500 config.guess: Update Haiku guesses commit f56a7140386d08a531bcfd444d632b28c61a6329 Author: Bruno Haible Date: Sun May 8 19:08:08 2022 +0200 config.guess (x86_64:Linux:*:*): Detect 32-bit ABI. 2023-04-20 Nick Clifton * SECURITY.txt: New file. * src-release.sh (DEVO_SUPPORT): Add SECURITY.txt. 2022-12-31 Nick Clifton * 2.40 binutils branch created. 2022-10-10 Nick Clifton * src-release.sh: Add "-r " option to create reproducible tarballs based upon a fixed timestamp of . * binutils/README-how-to-make-a-release: Add a line showing how to use -r when creating a binutils release. 2022-10-04 Nick Clifton * README-maintainer-mode: Add a minimum version of dejagnu requirement. 2022-09-08 Nick Clifton * README-maintainer-mode: Update minimum version of gettext required. @ text @d85 1 a85 1 #define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask d536 1 a536 1 abort (); d582 1 a582 1 if (strncmp (*strp, "0x0", 3) == 0 d649 1 a649 1 { d685 4 a688 4 if (*e == '`' && (*e+1) && ((*(e + 1) - '1') <= MAXARGS) && ((*(e + 1) - '1') <= narg)) d709 1 a709 1 else d734 2 a735 2 if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) { d746 1 a746 1 state = IN_TEXT; d755 1 a755 1 mark = in + 1; d796 1 a796 1 break; d798 1 a798 1 } d806 1 d810 1 a810 1 d813 1 a813 1 d852 1 a852 1 *strp_in = strstr (*strp_in, str); d855 1 a855 1 *strp_in += (str - hold); d863 1 a863 1 #define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); d948 1 a948 1 d952 1 a952 1 d961 2 a962 2 /* Print the + to indicate that the following copro insn is part of a vliw group. */ d964 1 a964 1 (*info->fprintf_func) (info->stream, " + "); d976 1 a976 1 d995 1 a995 1 break; d1028 1 a1028 1 d1041 1 a1041 1 cd->isas = 1 << ISA_EXT_COP1_64; d1069 5 a1073 7 /* The two functions mep_examine_vliw[32,64]_insns are used find out which vliw combinaion (16 bit core with 48 bit copro, 32 bit core with 32 bit copro, etc.) is present. Later on, when internally parallel coprocessors are handled, only these functions should need to be changed. At this time only the following combinations are supported: d1075 2 d1083 1 a1083 1 no 16 bit coprocessor insns have been specified. d1089 1 a1089 1 d1091 1 a1091 1 present (2nd coprocessor insn is cop2), but at this time it d1102 1 a1102 1 bfd_byte buf[CGEN_MAX_INSN_SIZE]; d1104 1 a1104 1 char indicatorcop32[2]; d1143 2 a1144 2 /* We have a 32 bit copro insn. */ corebuflength = 0; d1146 1 a1146 1 cop1buflength = 4; d1150 3 a1152 3 /* We have a 32 bit core. */ corebuflength = 4; cop1buflength = 0; d1232 2 a1233 2 /* We have a 64 bit copro insn. */ corebuflength = 0; d1235 1 a1235 1 cop1buflength = 8; d1239 3 a1241 3 /* We have a 32 bit core insn and a 32 bit copro insn. */ corebuflength = 4; cop1buflength = 4; d1293 2 a1294 2 { insn_list = CGEN_DIS_NEXT_INSN (insn_list); d1296 1 a1296 1 } a1455 14 /* mep_config_map is a variable sized array, so we do not know how big it is. The only safe way to check the index therefore is to iterate over the array. We do know that the last entry is all null. */ int i; for (i = 0; i <= mep_config_index; i++) if (mep_config_map[i].name == NULL) break; if (i < mep_config_index) { opcodes_error_handler (_("illegal MEP INDEX setting '%x' in ELF header e_flags field"), mep_config_index); mep_config_index = 0; } @ 1.1.1.5 log @Import binutils 2.45 (previous was 2.42) 2.45 Release Notes ------------------ Assembler: All sframe information generated by the assembler is now in compliance with the SFrame V2 specification. The assembler now supports .errif and .warnif directives, permitting user-controlled diagnostics with conditionals that are evaluated only at the end of assembly. The assembler predefines the symbol "GAS(version)". The assembler now supports the generation of SFrame stack trace information (.sframe) from CFI directives on s390 64-bit (s390x). For RISC-V, the ".option arch, -ext" format is deprecated due to its controversial use. For RISC-V, stop generating mapping symbols $x and replace with $x. The $x was defined to have the same ISA as previous $x, but now is defined to have the same ISA as elf architecture attribute. Once both used .option arch/rvc/norvc/push/pop directives (some code have different architectures with file attribute) and data directives in text, then the file need to be rebuilt since 2.45. The assembler supports the latest architecture extensions for the RISC-V, LoongArch and AArch64 architectures. Linker: The linker's --stats option can take an optional argument which if used is interpreted as a filename into which resource usage information should be stored. As an alternative mechanism the LD_STATS environment variable can also be used to achieve the same results. Resource usage information for various phases of the linking operation is now included in the report. If a map file is being produced then the information is also included there. The --no-stats option can be used to disable stat reporting, should it have been enabled. On s390 64-bit (s390x), generate SFrame stack trace information (.sframe) for the linker generated .plt section. On s390 32-bit, generate ".eh_frame" unwind information for the linker generated .plt section. Both features are enabled by default and can be disabled using linker option --no-ld-generated-unwind-info. On RISC-V, add new PLT formats, and GNU property merge rules for zicfiss and zicfilp extensions. On AVR, the default linker scripts now assert that the .progmem sections don't extend past 0xffff since they are accessed by means of LPM. For data in program memory that may be located past 0xffff, a .progmemx section should be used. On LoongArch, linker relaxation time complexity is no longer quadratic with respect to relocation counts. Linking time of large software should be improved. In addition R_LARCH_32_PCREL records are now checked for overflow. Other binary utilities: New versioned release of libsframe: libsframe.so.2. This release introduces versioned symbols with version node name LIBSFRAME_2.0. Some new symbols have been added to support the new flag SFRAME_F_FDE_FUNC_START_PCREL and retrieving flags from SFrame decoder and encoder objects: - Addition of sframe_decoder_get_flags, sframe_decoder_get_offsetof_fde_start_addr, sframe_encoder_get_flags, sframe_encoder_get_offsetof_fde_start_addr. This release also includes backward-incompatible ABI changes: - Removal of sframe_get_funcdesc_with_addr. - Change in the behavior of sframe_decoder_get_funcdesc_v2, sframe_encoder_add_funcdesc_v2 and sframe_encoder_write. For SFrame stack trace format, the function start address in each SFrame FDE has a changed encoding: The 32-bit signed integer now holds the offset of the start PC of the associated function from the sfde_func_start_address field itself (instead of the earlier where it was the offset from the start of the SFrame section itself). All SFrame sections generated by gas and ld now default to this new encoding, setting the (new) SFRAME_F_FDE_FUNC_START_PCREL flag. Relocatable SFrame links are now fixed. Readelf now recognizes RISC-V GNU_PROPERTY_RISCV_FEATURE_1_CFI_SS and GNU_PROPERTY_RISCV_FEATURE_1_CFI_LP_UNLABELED for zicfiss and zicfilp extensions. The LoongArch disassembler now properly accepts multiple disassembly options given by -M, such as "-M no-aliases,numeric". (Previously only the first option took effect.) 2.44 Release Notes ------------------ Assembler: Support for new architecture extensions for AArch64, Risc-V and x86. Linker: The default maximum page size was changed from 16KiB to 64KiB for LoongArch. This now supports mixed LTO and non-LTO object files in relocatable output. The ELF forms of the linker support a --image-base= option for compatibility with LLD. The --build-id= option now accepts an argument of "xx" which enables the use of the xxhash library. This produces a 128-bit hash and is 2-4x faster than md5 or sha1. The ELF linker option --package-metadata supports percent-encoded and %[string] encoded JSON payloads. Disassembler: The RISC-V disassembler now supports -M,max option like QEMU to dump instruction without checking architecture support as usual. GprofNG: Support added for hardware event counters for Neoverse-N1, Ampere-1, and Appliedmicro processors. Support for the Nios II target has been removed. 2.43 Release Notes ------------------ Assembler: * Add a .base64 directive to the assembler which allows base64 encoded binary data to be provided as strings. * Assembler macros as well as the bodies of .irp / .irpc / .rept can now use the syntax \+ to access the number of times a given macro has been executed. This is similar to the already existing \@@ syntax, except that the count is maintained on a per-macro basis. * References to FB and dollar labels, when supported, are no longer permitted in a radix other than 10. (Note that definitions of such labels were already thus restricted, except that leading zeroes were permitted). Linker: * Add support for DT_RELR type compressed runtime relocations for the AArch64 and LoongArch architectures. * Add --rosegment option which changes the -z separate-code option so that only one read-only segment is created (instead of two). * Add --section-ordering-file option to add extra mapping of input sections to output sections. * Add -plugin-save-temps to store plugin intermediate files permanently. Utilities: * Readelf will now display DT_RELR relocations in full detail. * Readelf now has a -j/--display-section option which takes the name or index of a section and displays its contents according to its type. The option can be used multiple times on the command line to display multiple sections. * When objdump or readelf are used to display the contents of a .eh_frame section they will now also display the contents of the .eh_frame_hdr section, if present. Gprofng: * Improved the support for hardware event counters: - Re-designed and streamlined the implementation. - Defined a common set of events for ARM processors. - Added specific events for AMD ZEN3 / ZEN4, and Intel Ice Lake processors. * Added a minimal support for RISC-V. General: * Target specific improvements for many architectures. @ text @a351 1 /* xgettext:no-c-format */ a547 1 /* xgettext:no-c-format */ @ 1.1.1.1.8.1 log @file mep.opc was added on branch tls-maxphys on 2014-08-19 23:52:30 +0000 @ text @d1 1669 @ 1.1.1.1.8.2 log @Rebase to HEAD as of a few days ago. @ text @a0 1669 /* MeP opcode support. -*- C -*- Copyright 2011 Free Software Foundation, Inc. Contributed by Red Hat Inc; This file is part of the GNU Binutils. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* -- opc.h */ #undef CGEN_DIS_HASH_SIZE #define CGEN_DIS_HASH_SIZE 1 #undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, insn) 0 #define CGEN_VERBOSE_ASSEMBLER_ERRORS typedef struct { char * name; int config_enum; unsigned cpu_flag; int big_endian; int vliw_bits; CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; CGEN_ATTR_VALUE_BITSET_TYPE core_isa; unsigned int option_mask; } mep_config_map_struct; extern mep_config_map_struct mep_config_map[]; extern int mep_config_index; extern void init_mep_all_core_isas_mask (void); extern void init_mep_all_cop_isas_mask (void); extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); #define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) #define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) #define MEP_OMASK (mep_config_map[mep_config_index].option_mask) #define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) #define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) #define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) #define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) #define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) #define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) #define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) #define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) #define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) /* begin-cop-ip-supported-defines */ #define MEP_IVC2_SUPPORTED 1 /* end-cop-ip-supported-defines */ extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); /* A mask for all ISAs executed by the core. */ #define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; #define MEP_INSN_CORE_P(insn) ( \ init_mep_all_core_isas_mask (), \ mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ ) /* A mask for all ISAs executed by a VLIW coprocessor. */ #define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; #define MEP_INSN_COP_P(insn) ( \ init_mep_all_cop_isas_mask (), \ mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ ) extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *); /* -- asm.c */ #include "elf/mep.h" #define CGEN_VALIDATE_INSN_SUPPORTED #define mep_cgen_insn_supported mep_cgen_insn_supported_asm const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_spreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_mep_align (CGEN_CPU_DESC, const char **, enum cgen_operand_type, long *); const char * parse_mep_alignu (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); static const char * parse_signed16 (CGEN_CPU_DESC, const char **, int, long *); static const char * parse_signed16_range (CGEN_CPU_DESC, const char **, int, long *) ATTRIBUTE_UNUSED; static const char * parse_unsigned16 (CGEN_CPU_DESC, const char **, int, unsigned long *); static const char * parse_unsigned16_range (CGEN_CPU_DESC, const char **, int, unsigned long *) ATTRIBUTE_UNUSED; static const char * parse_lo16 (CGEN_CPU_DESC, const char **, int, long *, long); static const char * parse_unsigned7 (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); static const char * parse_zero (CGEN_CPU_DESC, const char **, int, long *); const char * parse_csrn (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; unsigned long value; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (!err) return NULL; err = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, & value); if (err) return err; *field = value; return NULL; } /* begin-cop-ip-parse-handlers */ static const char * parse_ivc2_cr (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *) ATTRIBUTE_UNUSED; static const char * parse_ivc2_cr (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long *field) { return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field); } static const char * parse_ivc2_ccr (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *) ATTRIBUTE_UNUSED; static const char * parse_ivc2_ccr (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long *field) { return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field); } /* end-cop-ip-parse-handlers */ const char * parse_tpreg (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (err) return err; if (*field != 13) return _("Only $tp or $13 allowed for this opcode"); return NULL; } const char * parse_spreg (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (err) return err; if (*field != 15) return _("Only $sp or $15 allowed for this opcode"); return NULL; } const char * parse_mep_align (CGEN_CPU_DESC cd, const char ** strp, enum cgen_operand_type type, long *field) { long lsbs = 0; const char *err; switch (type) { case MEP_OPERAND_PCREL8A2: case MEP_OPERAND_PCREL12A2: case MEP_OPERAND_PCREL17A2: case MEP_OPERAND_PCREL24A2: err = cgen_parse_signed_integer (cd, strp, type, field); break; case MEP_OPERAND_PCABS24A2: case MEP_OPERAND_UDISP7: case MEP_OPERAND_UDISP7A2: case MEP_OPERAND_UDISP7A4: case MEP_OPERAND_UIMM7A4: case MEP_OPERAND_ADDR24A4: err = cgen_parse_unsigned_integer (cd, strp, type, (unsigned long *) field); break; default: abort(); } if (err) return err; switch (type) { case MEP_OPERAND_UDISP7: lsbs = 0; break; case MEP_OPERAND_PCREL8A2: case MEP_OPERAND_PCREL12A2: case MEP_OPERAND_PCREL17A2: case MEP_OPERAND_PCREL24A2: case MEP_OPERAND_PCABS24A2: case MEP_OPERAND_UDISP7A2: lsbs = *field & 1; break; case MEP_OPERAND_UDISP7A4: case MEP_OPERAND_UIMM7A4: case MEP_OPERAND_ADDR24A4: lsbs = *field & 3; break; lsbs = *field & 7; break; default: /* Safe assumption? */ abort (); } if (lsbs) return "Value is not aligned enough"; return NULL; } const char * parse_mep_alignu (CGEN_CPU_DESC cd, const char ** strp, enum cgen_operand_type type, unsigned long *field) { return parse_mep_align (cd, strp, type, (long *) field); } /* Handle %lo(), %tpoff(), %sdaoff(), %hi(), and other signed constants in a signed context. */ static const char * parse_signed16 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { return parse_lo16 (cd, strp, opindex, valuep, 1); } static const char * parse_lo16 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep, long signedp) { const char *errmsg; enum cgen_parse_operand_result result_type; bfd_vma value; if (strncasecmp (*strp, "%lo(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value &= 0xffff; if (signedp) *valuep = (long)(short) value; else *valuep = value; return errmsg; } if (strncasecmp (*strp, "%hi(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value = (value + 0x8000) >> 16; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%uhi(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value = value >> 16; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%sdaoff(", 8) == 0) { *strp += 8; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, NULL, & value); if (**strp != ')') return _("missing `)'"); ++*strp; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%tpoff(", 7) == 0) { *strp += 7; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, NULL, & value); if (**strp != ')') return _("missing `)'"); ++*strp; *valuep = value; return errmsg; } if (**strp == '%') return _("invalid %function() here"); return cgen_parse_signed_integer (cd, strp, opindex, valuep); } static const char * parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp, int opindex, unsigned long *valuep) { return parse_lo16 (cd, strp, opindex, (long *) valuep, 0); } static const char * parse_signed16_range (CGEN_CPU_DESC cd, const char **strp, int opindex, signed long *valuep) { const char *errmsg = 0; signed long value; errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (value < -32768 || value > 32767) return _("Immediate is out of range -32768 to 32767"); *valuep = value; return 0; } static const char * parse_unsigned16_range (CGEN_CPU_DESC cd, const char **strp, int opindex, unsigned long *valuep) { const char *errmsg = 0; unsigned long value; errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (value > 65535) return _("Immediate is out of range 0 to 65535"); *valuep = value; return 0; } /* A special case of parse_signed16 which accepts only the value zero. */ static const char * parse_zero (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; bfd_vma value; /*fprintf(stderr, "dj: signed parse opindex `%s'\n", *strp);*/ /* Prevent ($ry) from being attempted as an expression on 'sw $rx,($ry)'. It will fail and cause ry to be listed as an undefined symbol in the listing. */ if (strncmp (*strp, "($", 2) == 0) return "not zero"; /* any string will do -- will never be seen. */ if (strncasecmp (*strp, "%lo(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%hi(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%uhi(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%sdaoff(", 8) == 0) { *strp += 8; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%tpoff(", 7) == 0) { *strp += 7; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (**strp == '%') return "invalid %function() here"; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_NONE, &result_type, &value); if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ return errmsg; } static const char * parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp, enum cgen_operand_type opindex, unsigned long *valuep) { const char *errmsg; bfd_vma value; /* fprintf(stderr, "dj: unsigned7 parse `%s'\n", *strp); */ if (strncasecmp (*strp, "%tpoff(", 7) == 0) { int reloc; *strp += 7; switch (opindex) { case MEP_OPERAND_UDISP7: reloc = BFD_RELOC_MEP_TPREL7; break; case MEP_OPERAND_UDISP7A2: reloc = BFD_RELOC_MEP_TPREL7A2; break; case MEP_OPERAND_UDISP7A4: reloc = BFD_RELOC_MEP_TPREL7A4; break; default: /* Safe assumption? */ abort (); } errmsg = cgen_parse_address (cd, strp, opindex, reloc, NULL, &value); if (**strp != ')') return "missing `)'"; ++*strp; *valuep = value; return errmsg; } if (**strp == '%') return _("invalid %function() here"); return parse_mep_alignu (cd, strp, opindex, valuep); } static ATTRIBUTE_UNUSED const char * parse_cdisp10 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { const char *errmsg = 0; signed long value; long have_zero = 0; int wide = 0; int alignment; switch (opindex) { case MEP_OPERAND_CDISP10A4: alignment = 2; break; case MEP_OPERAND_CDISP10A2: alignment = 1; break; case MEP_OPERAND_CDISP10: default: alignment = 0; break; } if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5) wide = 1; if (strncmp (*strp, "0x0", 3) == 0 || (**strp == '0' && *(*strp + 1) != 'x')) have_zero = 1; errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (wide) { if (value < -512 || value > 511) return _("Immediate is out of range -512 to 511"); } else { if (value < -128 || value > 127) return _("Immediate is out of range -128 to 127"); } if (value & ((1<>16) & 0xffff)" }, */ /*{ "lo", "(`1 & 0xffff)" }, */ /*{ "sdaoff", "((`1-__sdabase) & 0x7f)"}, */ /*{ "tpoff", "((`1-__tpbase) & 0x7f)"}, */ { 0,0 } }; static char * expand_string (const char *, int); static const char * mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); static char * str_append (char *dest, const char *input, int len) { char *new_dest; int oldlen; if (len == 0) return dest; /* printf("str_append: <<%s>>, <<%s>>, %d\n", dest, input, len); */ oldlen = (dest ? strlen(dest) : 0); new_dest = realloc (dest, oldlen + len + 1); memset (new_dest + oldlen, 0, len + 1); return strncat (new_dest, input, len); } static macro * lookup_macro (const char *name) { macro *m; for (m = macros; m->name; ++m) if (strncmp (m->name, name, strlen(m->name)) == 0) return m; return 0; } static char * expand_macro (arg *args, int narg, macro *mac) { char *result = 0, *rescanned_result = 0; char *e = mac->expansion; char *mark = e; int mac_arg = 0; /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ while (*e) { if (*e == '`' && (*e+1) && ((*(e + 1) - '1') <= MAXARGS) && ((*(e + 1) - '1') <= narg)) { result = str_append (result, mark, e - mark); mac_arg = (*(e + 1) - '1'); /* printf("replacing `%d with %s\n", mac_arg+1, args[mac_arg].start); */ result = str_append (result, args[mac_arg].start, args[mac_arg].len); ++e; mark = e+1; } ++e; } if (mark != e) result = str_append (result, mark, e - mark); if (result) { rescanned_result = expand_string (result, 0); free (result); return rescanned_result; } else return result; } #define IN_TEXT 0 #define IN_ARGS 1 static char * expand_string (const char *in, int first_only) { int num_expansions = 0; int depth = 0; int narg = -1; arg args[MAXARGS]; int state = IN_TEXT; const char *mark = in; macro *pmacro = NULL; char *expansion = 0; char *result = 0; while (*in) { switch (state) { case IN_TEXT: if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) { pmacro = lookup_macro (in + 1); if (pmacro) { /* printf("entering state %d at '%s'...\n", state, in); */ result = str_append (result, mark, in - mark); mark = in; in += 1 + strlen (pmacro->name); while (*in == ' ') ++in; if (*in != '(') { state = IN_TEXT; pmacro = NULL; } else { state = IN_ARGS; narg = 0; args[narg].start = in + 1; args[narg].len = 0; mark = in + 1; } } } break; case IN_ARGS: if (depth == 0) { switch (*in) { case ',': narg++; args[narg].start = (in + 1); args[narg].len = 0; break; case ')': state = IN_TEXT; /* printf("entering state %d at '%s'...\n", state, in); */ if (pmacro) { expansion = 0; expansion = expand_macro (args, narg, pmacro); num_expansions++; if (expansion) { result = str_append (result, expansion, strlen (expansion)); free (expansion); } } else { result = str_append (result, mark, in - mark); } pmacro = NULL; mark = in + 1; break; case '(': depth++; default: args[narg].len++; break; } } else { if (*in == ')') depth--; if (narg > -1) args[narg].len++; } } ++in; } if (mark != in) result = str_append (result, mark, in - mark); return result; } #undef IN_ARGS #undef IN_TEXT #undef MAXARGS /* END LIGHTWEIGHT MACRO PROCESSOR. */ const char * mep_cgen_parse_operand (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); const char * mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex, const char ** strp_in, CGEN_FIELDS * fields) { const char * errmsg = NULL; char *str = 0, *hold = 0; const char **strp = 0; /* Set up a new pointer to macro-expanded string. */ str = expand_string (*strp_in, 1); /* fprintf (stderr, " expanded <<%s>> to <<%s>>\n", *strp_in, str); */ hold = str; strp = (const char **)(&str); errmsg = mep_cgen_parse_operand (cd, opindex, strp, fields); /* Now work out the advance. */ if (strlen (str) == 0) *strp_in += strlen (*strp_in); else { if (strstr (*strp_in, str)) /* A macro-expansion was pulled off the front. */ *strp_in = strstr (*strp_in, str); else /* A non-macro-expansion was pulled off the front. */ *strp_in += (str - hold); } if (hold) free (hold); return errmsg; } #define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); /* -- dis.c */ #include "elf/mep.h" #include "elf-bfd.h" #define CGEN_VALIDATE_INSN_SUPPORTED static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); static void print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, unsigned int flags ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "$tp"); } static void print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, unsigned int flags ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "$sp"); } /* begin-cop-ip-print-handlers */ static void print_ivc2_cr (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; static void print_ivc2_cr (CGEN_CPU_DESC cd, void *dis_info, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long value, unsigned int attrs) { print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs); } static void print_ivc2_ccr (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; static void print_ivc2_ccr (CGEN_CPU_DESC cd, void *dis_info, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long value, unsigned int attrs) { print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs); } /* end-cop-ip-print-handlers */ /************************************************************\ *********************** Experimental ************************* \************************************************************/ #undef CGEN_PRINT_INSN #define CGEN_PRINT_INSN mep_print_insn static int mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, bfd_byte *buf, int corelength, int copro1length, int copro2length ATTRIBUTE_UNUSED) { int i; int status = 0; /* char insnbuf[CGEN_MAX_INSN_SIZE]; */ bfd_byte insnbuf[64]; /* If corelength > 0 then there is a core insn present. It will be at the beginning of the buffer. After printing the core insn, we need to print the + on the next line. */ if (corelength > 0) { int my_status = 0; for (i = 0; i < corelength; i++ ) insnbuf[i] = buf[i]; cd->isas = & MEP_CORE_ISA; my_status = print_insn (cd, pc, info, insnbuf, corelength); if (my_status != corelength) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = corelength; } status += my_status; /* Print the + to indicate that the following copro insn is */ /* part of a vliw group. */ if (copro1length > 0) (*info->fprintf_func) (info->stream, " + "); } /* Now all that is left to be processed is the coprocessor insns In vliw mode, there will always be one. Its positioning will be from byte corelength to byte corelength+copro1length -1. No need to check for existence. Also, the first vliw insn, will, as spec'd, always be at least as long as the core insn so we don't need to flush the buffer. */ if (copro1length > 0) { int my_status = 0; for (i = corelength; i < corelength + copro1length; i++ ) insnbuf[i - corelength] = buf[i]; switch (copro1length) { case 0: break; case 2: cd->isas = & MEP_COP16_ISA; break; case 4: cd->isas = & MEP_COP32_ISA; break; case 6: cd->isas = & MEP_COP48_ISA; break; case 8: cd->isas = & MEP_COP64_ISA; break; default: /* Shouldn't be anything but 16,32,48,64. */ break; } my_status = print_insn (cd, pc, info, insnbuf, copro1length); if (my_status != copro1length) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = copro1length; } status += my_status; } #if 0 /* Now we need to process the second copro insn if it exists. We have no guarantee that the second copro insn will be longer than the first, so we have to flush the buffer if we are have a second copro insn to process. If present, this insn will be in the position from byte corelength+copro1length to byte corelength+copro1length+copro2length-1 (which better equal 8 or else we're in big trouble. */ if (copro2length > 0) { int my_status = 0; for (i = 0; i < 64 ; i++) insnbuf[i] = 0; for (i = corelength + copro1length; i < 64; i++) insnbuf[i - (corelength + copro1length)] = buf[i]; switch (copro2length) { case 2: cd->isas = 1 << ISA_EXT_COP1_16; break; case 4: cd->isas = 1 << ISA_EXT_COP1_32; break; case 6: cd->isas = 1 << ISA_EXT_COP1_48; break; case 8: cd->isas = 1 << ISA_EXT_COP1_64; break; default: /* Shouldn't be anything but 16,32,48,64. */ break; } my_status = print_insn (cd, pc, info, insnbuf, copro2length); if (my_status != copro2length) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = copro2length; } status += my_status; } #endif /* Status should now be the number of bytes that were printed which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */ if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8))) return -1; else return status; } /* The two functions mep_examine_vliw[32,64]_insns are used find out which vliw combinaion (16 bit core with 48 bit copro, 32 bit core with 32 bit copro, etc.) is present. Later on, when internally parallel coprocessors are handled, only these functions should need to be changed. At this time only the following combinations are supported: VLIW32 Mode: 16 bit core insn (core) and 16 bit coprocessor insn (cop1) 32 bit core insn (core) 32 bit coprocessor insn (cop1) Note: As of this time, I do not believe we have enough information to distinguish a 32 bit core insn from a 32 bit cop insn. Also, no 16 bit coprocessor insns have been specified. VLIW64 Mode: 16 bit core insn (core) and 48 bit coprocessor insn (cop1) 32 bit core insn (core) and 32 bit coprocessor insn (cop1) 64 bit coprocessor insn (cop1) The framework for an internally parallel coprocessor is also present (2nd coprocessor insn is cop2), but at this time it is not used. This only appears to be valid in VLIW64 mode. */ static int mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int buflength; int corebuflength; int cop1buflength; int cop2buflength; bfd_byte buf[CGEN_MAX_INSN_SIZE]; char indicator16[1]; char indicatorcop32[2]; /* At this time we're not supporting internally parallel coprocessors, so cop2buflength will always be 0. */ cop2buflength = 0; /* Read in 32 bits. */ buflength = 4; /* VLIW insn spans 4 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } /* Put the big endian representation of the bytes to be examined in the temporary buffers for examination. */ if (info->endian == BFD_ENDIAN_BIG) { indicator16[0] = buf[0]; indicatorcop32[0] = buf[0]; indicatorcop32[1] = buf[1]; } else { indicator16[0] = buf[1]; indicatorcop32[0] = buf[1]; indicatorcop32[1] = buf[0]; } /* If the two high order bits are 00, 01 or 10, we have a 16 bit core insn and a 48 bit copro insn. */ if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) { if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) { /* We have a 32 bit copro insn. */ corebuflength = 0; /* All 4 4ytes are one copro insn. */ cop1buflength = 4; } else { /* We have a 32 bit core. */ corebuflength = 4; cop1buflength = 0; } } else { /* We have a 16 bit core insn and a 16 bit copro insn. */ corebuflength = 2; cop1buflength = 2; } /* Now we have the distrubution set. Print them out. */ status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, cop1buflength, cop2buflength); return status; } static int mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int buflength; int corebuflength; int cop1buflength; int cop2buflength; bfd_byte buf[CGEN_MAX_INSN_SIZE]; char indicator16[1]; char indicator64[4]; /* At this time we're not supporting internally parallel coprocessors, so cop2buflength will always be 0. */ cop2buflength = 0; /* Read in 64 bits. */ buflength = 8; /* VLIW insn spans 8 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } /* We have all 64 bits in the buffer now. We have to figure out what combination of instruction sizes are present. The two high order bits will indicate whether or not we have a 16 bit core insn or not. If not, then we have to look at the 7,8th bytes to tell whether we have 64 bit copro insn or a 32 bit core insn with a 32 bit copro insn. Endianness will make a difference here. */ /* Put the big endian representation of the bytes to be examined in the temporary buffers for examination. */ /* indicator16[0] = buf[0]; */ if (info->endian == BFD_ENDIAN_BIG) { indicator16[0] = buf[0]; indicator64[0] = buf[0]; indicator64[1] = buf[1]; indicator64[2] = buf[2]; indicator64[3] = buf[3]; } else { indicator16[0] = buf[1]; indicator64[0] = buf[1]; indicator64[1] = buf[0]; indicator64[2] = buf[3]; indicator64[3] = buf[2]; } /* If the two high order bits are 00, 01 or 10, we have a 16 bit core insn and a 48 bit copro insn. */ if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) { if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) { /* We have a 64 bit copro insn. */ corebuflength = 0; /* All 8 bytes are one copro insn. */ cop1buflength = 8; } else { /* We have a 32 bit core insn and a 32 bit copro insn. */ corebuflength = 4; cop1buflength = 4; } } else { /* We have a 16 bit core insn and a 48 bit copro insn. */ corebuflength = 2; cop1buflength = 6; } /* Now we have the distrubution set. Print them out. */ status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, cop1buflength, cop2buflength); return status; } #ifdef MEP_IVC2_SUPPORTED static int print_slot_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, SLOTS_ATTR slot, bfd_byte *buf) { const CGEN_INSN_LIST *insn_list; CGEN_INSN_INT insn_value; CGEN_EXTRACT_INFO ex_info; insn_value = cgen_get_insn_value (cd, buf, 32); /* Fill in ex_info fields like read_insn would. Don't actually call read_insn, since the incoming buffer is already read (and possibly modified a la m32r). */ ex_info.valid = (1 << 8) - 1; ex_info.dis_info = info; ex_info.insn_bytes = buf; /* The instructions are stored in hash lists. Pick the first one and keep trying until we find the right one. */ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); while (insn_list != NULL) { const CGEN_INSN *insn = insn_list->insn; CGEN_FIELDS fields; int length; if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) { insn_list = CGEN_DIS_NEXT_INSN (insn_list); continue; } if ((insn_value & CGEN_INSN_BASE_MASK (insn)) == CGEN_INSN_BASE_VALUE (insn)) { /* Printing is handled in two passes. The first pass parses the machine insn and extracts the fields. The second pass prints them. */ length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value, &fields, pc); /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); /* Length is in bits, result is in bytes. */ return length / 8; } } insn_list = CGEN_DIS_NEXT_INSN (insn_list); } if (slot == SLOTS_P0S) (*info->fprintf_func) (info->stream, "*unknown-p0s*"); else if (slot == SLOTS_P0) (*info->fprintf_func) (info->stream, "*unknown-p0*"); else if (slot == SLOTS_P1) (*info->fprintf_func) (info->stream, "*unknown-p1*"); else if (slot == SLOTS_C3) (*info->fprintf_func) (info->stream, "*unknown-c3*"); return 0; } static int mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED) { int status; int buflength; bfd_byte buf[8]; bfd_byte insn[8]; int e; /* Read in 64 bits. */ buflength = 8; /* VLIW insn spans 8 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } if (info->endian == BFD_ENDIAN_LITTLE) e = 1; else e = 0; if (((unsigned char)buf[0^e] & 0xf0) < 0xc0) { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V1 [-----core-----][--------p0s-------][------------p1------------] */ print_insn (cd, pc, info, buf, 2); insn[0^e] = 0; insn[1^e] = buf[2^e]; insn[2^e] = buf[3^e]; insn[3^e] = buf[4^e] & 0xf0; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P0S, insn); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07) { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */ /* 00000000111111112222222233333333 */ insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4; insn[1^e] = buf[2^e]; insn[2^e] = buf[3^e]; insn[3^e] = buf[4^e] & 0xf0; print_slot_insn (cd, pc, info, SLOTS_P0, insn); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } else { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V2 [-------------core-------------]xxxx[------------p1------------] */ print_insn (cd, pc, info, buf, 4); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } return 8; } #endif /* MEP_IVC2_SUPPORTED */ /* This is a hack. SID calls this to update the disassembler as the CPU changes modes. */ static int mep_ivc2_disassemble_p = 0; static int mep_ivc2_vliw_disassemble_p = 0; void mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx); void mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx) { mep_ivc2_disassemble_p = ivc2_p; mep_ivc2_vliw_disassemble_p = vliw_p; mep_config_index = cfg_idx; } static int mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int cop_type; int ivc2 = 0; static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL; if (ivc2_core_isa == NULL) { /* IVC2 has some core-only coprocessor instructions. We use COP32 to flag those, and COP64 for the VLIW ones, since they have the same names. */ ivc2_core_isa = cgen_bitset_create (MAX_ISAS); } /* Extract and adapt to configuration number, if available. */ if (info->section && info->section->owner) { bfd *abfd = info->section->owner; mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; if (cop_type == EF_MEP_COP_IVC2) ivc2 = 1; } /* Picking the right ISA bitmask for the current context is tricky. */ if (info->section) { if (info->section->flags & SEC_MEP_VLIW) { #ifdef MEP_IVC2_SUPPORTED if (ivc2) { /* ivc2 has its own way of selecting its functions. */ cd->isas = & MEP_CORE_ISA; status = mep_examine_ivc2_insns (cd, pc, info); } else #endif /* Are we in 32 or 64 bit vliw mode? */ if (MEP_VLIW64) status = mep_examine_vliw64_insns (cd, pc, info); else status = mep_examine_vliw32_insns (cd, pc, info); /* Both the above branches set their own isa bitmasks. */ } else { if (ivc2) { cgen_bitset_clear (ivc2_core_isa); cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa); cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa); cd->isas = ivc2_core_isa; } else cd->isas = & MEP_CORE_ISA; status = default_print_insn (cd, pc, info); } } else /* sid or gdb */ { #ifdef MEP_IVC2_SUPPORTED if (mep_ivc2_disassemble_p) { if (mep_ivc2_vliw_disassemble_p) { cd->isas = & MEP_CORE_ISA; status = mep_examine_ivc2_insns (cd, pc, info); return status; } else { if (ivc2) cd->isas = ivc2_core_isa; } } #endif status = default_print_insn (cd, pc, info); } return status; } /* -- opc.c */ #include "elf/mep.h" /* A mask for all ISAs executed by the core. */ CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask = {0, 0}; void init_mep_all_core_isas_mask (void) { if (mep_all_core_isas_mask.length != 0) return; cgen_bitset_init (& mep_all_core_isas_mask, ISA_MAX); cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP); /* begin-all-core-isas */ cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1); /* end-all-core-isas */ } CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask = {0, 0}; void init_mep_all_cop_isas_mask (void) { if (mep_all_cop_isas_mask.length != 0) return; cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX); /* begin-all-cop-isas */ cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_16); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_32); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_48); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_64); /* end-all-cop-isas */ } int mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *isa_mask) { CGEN_BITSET insn_isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); return cgen_bitset_intersect_p (& insn_isas, isa_mask); } #define OPTION_MASK \ ( (1 << CGEN_INSN_OPTIONAL_BIT_INSN) \ | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN) \ | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) \ | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) \ | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) \ | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) \ | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) ) mep_config_map_struct mep_config_map[] = { /* config-map-start */ /* Default entry: first module, with all options enabled. */ { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, 0 | (1 << CGEN_INSN_OPTIONAL_CP_INSN) | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) | (1 << CGEN_INSN_OPTIONAL_BIT_INSN) | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) }, /* config-map-end */ { 0, 0, 0, 0, 0, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, 0 } }; int mep_config_index = 0; static int check_configured_mach (int machs) { /* All base insns are supported. */ int mach = 1 << MACH_BASE; switch (MEP_CPU & EF_MEP_CPU_MASK) { case EF_MEP_CPU_C2: case EF_MEP_CPU_C3: mach |= (1 << MACH_MEP); break; case EF_MEP_CPU_H1: mach |= (1 << MACH_H1); break; case EF_MEP_CPU_C5: mach |= (1 << MACH_MEP); mach |= (1 << MACH_C5); break; default: break; } return machs & mach; } int mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int iconfig = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG); int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); int ok1; int ok2; int ok3; /* If the insn has an option bit set that we don't want, reject it. */ if (CGEN_INSN_ATTRS (insn)->bool_ & OPTION_MASK & ~MEP_OMASK) return 0; /* If attributes are absent, assume no restriction. */ if (machs == 0) machs = ~0; ok1 = ((machs & cd->machs) && cgen_bitset_intersect_p (& isas, cd->isas)); /* If the insn is config-specific, make sure it matches. */ ok2 = (iconfig == 0 || iconfig == MEP_CONFIG); /* Make sure the insn is supported by the configured mach */ ok3 = check_configured_mach (machs); return (ok1 && ok2 && ok3); } int mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { #ifdef MEP_IVC2_SUPPORTED /* If we're assembling VLIW packets, ignore the 12-bit BSR as we can't relax that. The 24-bit BSR is matched instead. */ if (insn->base->num == MEP_INSN_BSR12 && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64)) return 0; #endif return mep_cgen_insn_supported (cd, insn); } @ 1.1.1.1.4.1 log @file mep.opc was added on branch yamt-pagecache on 2014-05-22 15:54:15 +0000 @ text @d1 1669 @ 1.1.1.1.4.2 log @sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments") @ text @a0 1669 /* MeP opcode support. -*- C -*- Copyright 2011 Free Software Foundation, Inc. Contributed by Red Hat Inc; This file is part of the GNU Binutils. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* -- opc.h */ #undef CGEN_DIS_HASH_SIZE #define CGEN_DIS_HASH_SIZE 1 #undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, insn) 0 #define CGEN_VERBOSE_ASSEMBLER_ERRORS typedef struct { char * name; int config_enum; unsigned cpu_flag; int big_endian; int vliw_bits; CGEN_ATTR_VALUE_BITSET_TYPE cop16_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop32_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop48_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop64_isa; CGEN_ATTR_VALUE_BITSET_TYPE cop_isa; CGEN_ATTR_VALUE_BITSET_TYPE core_isa; unsigned int option_mask; } mep_config_map_struct; extern mep_config_map_struct mep_config_map[]; extern int mep_config_index; extern void init_mep_all_core_isas_mask (void); extern void init_mep_all_cop_isas_mask (void); extern CGEN_ATTR_VALUE_BITSET_TYPE mep_cop_isa (void); #define MEP_CONFIG (mep_config_map[mep_config_index].config_enum) #define MEP_CPU (mep_config_map[mep_config_index].cpu_flag) #define MEP_OMASK (mep_config_map[mep_config_index].option_mask) #define MEP_VLIW (mep_config_map[mep_config_index].vliw_bits > 0) #define MEP_VLIW32 (mep_config_map[mep_config_index].vliw_bits == 32) #define MEP_VLIW64 (mep_config_map[mep_config_index].vliw_bits == 64) #define MEP_COP16_ISA (mep_config_map[mep_config_index].cop16_isa) #define MEP_COP32_ISA (mep_config_map[mep_config_index].cop32_isa) #define MEP_COP48_ISA (mep_config_map[mep_config_index].cop48_isa) #define MEP_COP64_ISA (mep_config_map[mep_config_index].cop64_isa) #define MEP_COP_ISA (mep_config_map[mep_config_index].cop_isa) #define MEP_CORE_ISA (mep_config_map[mep_config_index].core_isa) /* begin-cop-ip-supported-defines */ #define MEP_IVC2_SUPPORTED 1 /* end-cop-ip-supported-defines */ extern int mep_insn_supported_by_isa (const CGEN_INSN *, CGEN_ATTR_VALUE_BITSET_TYPE *); /* A mask for all ISAs executed by the core. */ #define MEP_ALL_CORE_ISAS_MASK mep_all_core_isas_mask extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask; #define MEP_INSN_CORE_P(insn) ( \ init_mep_all_core_isas_mask (), \ mep_insn_supported_by_isa (insn, & MEP_ALL_CORE_ISAS_MASK) \ ) /* A mask for all ISAs executed by a VLIW coprocessor. */ #define MEP_ALL_COP_ISAS_MASK mep_all_cop_isas_mask extern CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask; #define MEP_INSN_COP_P(insn) ( \ init_mep_all_cop_isas_mask (), \ mep_insn_supported_by_isa (insn, & MEP_ALL_COP_ISAS_MASK) \ ) extern int mep_cgen_insn_supported (CGEN_CPU_DESC, const CGEN_INSN *); extern int mep_cgen_insn_supported_asm (CGEN_CPU_DESC, const CGEN_INSN *); /* -- asm.c */ #include "elf/mep.h" #define CGEN_VALIDATE_INSN_SUPPORTED #define mep_cgen_insn_supported mep_cgen_insn_supported_asm const char * parse_csrn (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_tpreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_spreg (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); const char * parse_mep_align (CGEN_CPU_DESC, const char **, enum cgen_operand_type, long *); const char * parse_mep_alignu (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); static const char * parse_signed16 (CGEN_CPU_DESC, const char **, int, long *); static const char * parse_signed16_range (CGEN_CPU_DESC, const char **, int, long *) ATTRIBUTE_UNUSED; static const char * parse_unsigned16 (CGEN_CPU_DESC, const char **, int, unsigned long *); static const char * parse_unsigned16_range (CGEN_CPU_DESC, const char **, int, unsigned long *) ATTRIBUTE_UNUSED; static const char * parse_lo16 (CGEN_CPU_DESC, const char **, int, long *, long); static const char * parse_unsigned7 (CGEN_CPU_DESC, const char **, enum cgen_operand_type, unsigned long *); static const char * parse_zero (CGEN_CPU_DESC, const char **, int, long *); const char * parse_csrn (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; unsigned long value; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (!err) return NULL; err = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_CSRN_IDX, & value); if (err) return err; *field = value; return NULL; } /* begin-cop-ip-parse-handlers */ static const char * parse_ivc2_cr (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *) ATTRIBUTE_UNUSED; static const char * parse_ivc2_cr (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long *field) { return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_cr_ivc2, field); } static const char * parse_ivc2_ccr (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *) ATTRIBUTE_UNUSED; static const char * parse_ivc2_ccr (CGEN_CPU_DESC cd, const char **strp, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long *field) { return cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, field); } /* end-cop-ip-parse-handlers */ const char * parse_tpreg (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (err) return err; if (*field != 13) return _("Only $tp or $13 allowed for this opcode"); return NULL; } const char * parse_spreg (CGEN_CPU_DESC cd, const char ** strp, CGEN_KEYWORD *keyword_table, long *field) { const char *err; err = cgen_parse_keyword (cd, strp, keyword_table, field); if (err) return err; if (*field != 15) return _("Only $sp or $15 allowed for this opcode"); return NULL; } const char * parse_mep_align (CGEN_CPU_DESC cd, const char ** strp, enum cgen_operand_type type, long *field) { long lsbs = 0; const char *err; switch (type) { case MEP_OPERAND_PCREL8A2: case MEP_OPERAND_PCREL12A2: case MEP_OPERAND_PCREL17A2: case MEP_OPERAND_PCREL24A2: err = cgen_parse_signed_integer (cd, strp, type, field); break; case MEP_OPERAND_PCABS24A2: case MEP_OPERAND_UDISP7: case MEP_OPERAND_UDISP7A2: case MEP_OPERAND_UDISP7A4: case MEP_OPERAND_UIMM7A4: case MEP_OPERAND_ADDR24A4: err = cgen_parse_unsigned_integer (cd, strp, type, (unsigned long *) field); break; default: abort(); } if (err) return err; switch (type) { case MEP_OPERAND_UDISP7: lsbs = 0; break; case MEP_OPERAND_PCREL8A2: case MEP_OPERAND_PCREL12A2: case MEP_OPERAND_PCREL17A2: case MEP_OPERAND_PCREL24A2: case MEP_OPERAND_PCABS24A2: case MEP_OPERAND_UDISP7A2: lsbs = *field & 1; break; case MEP_OPERAND_UDISP7A4: case MEP_OPERAND_UIMM7A4: case MEP_OPERAND_ADDR24A4: lsbs = *field & 3; break; lsbs = *field & 7; break; default: /* Safe assumption? */ abort (); } if (lsbs) return "Value is not aligned enough"; return NULL; } const char * parse_mep_alignu (CGEN_CPU_DESC cd, const char ** strp, enum cgen_operand_type type, unsigned long *field) { return parse_mep_align (cd, strp, type, (long *) field); } /* Handle %lo(), %tpoff(), %sdaoff(), %hi(), and other signed constants in a signed context. */ static const char * parse_signed16 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { return parse_lo16 (cd, strp, opindex, valuep, 1); } static const char * parse_lo16 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep, long signedp) { const char *errmsg; enum cgen_parse_operand_result result_type; bfd_vma value; if (strncasecmp (*strp, "%lo(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value &= 0xffff; if (signedp) *valuep = (long)(short) value; else *valuep = value; return errmsg; } if (strncasecmp (*strp, "%hi(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value = (value + 0x8000) >> 16; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%uhi(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, & result_type, & value); if (**strp != ')') return _("missing `)'"); ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) value = value >> 16; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%sdaoff(", 8) == 0) { *strp += 8; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, NULL, & value); if (**strp != ')') return _("missing `)'"); ++*strp; *valuep = value; return errmsg; } if (strncasecmp (*strp, "%tpoff(", 7) == 0) { *strp += 7; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, NULL, & value); if (**strp != ')') return _("missing `)'"); ++*strp; *valuep = value; return errmsg; } if (**strp == '%') return _("invalid %function() here"); return cgen_parse_signed_integer (cd, strp, opindex, valuep); } static const char * parse_unsigned16 (CGEN_CPU_DESC cd, const char **strp, int opindex, unsigned long *valuep) { return parse_lo16 (cd, strp, opindex, (long *) valuep, 0); } static const char * parse_signed16_range (CGEN_CPU_DESC cd, const char **strp, int opindex, signed long *valuep) { const char *errmsg = 0; signed long value; errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (value < -32768 || value > 32767) return _("Immediate is out of range -32768 to 32767"); *valuep = value; return 0; } static const char * parse_unsigned16_range (CGEN_CPU_DESC cd, const char **strp, int opindex, unsigned long *valuep) { const char *errmsg = 0; unsigned long value; errmsg = cgen_parse_unsigned_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (value > 65535) return _("Immediate is out of range 0 to 65535"); *valuep = value; return 0; } /* A special case of parse_signed16 which accepts only the value zero. */ static const char * parse_zero (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { const char *errmsg; enum cgen_parse_operand_result result_type; bfd_vma value; /*fprintf(stderr, "dj: signed parse opindex `%s'\n", *strp);*/ /* Prevent ($ry) from being attempted as an expression on 'sw $rx,($ry)'. It will fail and cause ry to be listed as an undefined symbol in the listing. */ if (strncmp (*strp, "($", 2) == 0) return "not zero"; /* any string will do -- will never be seen. */ if (strncasecmp (*strp, "%lo(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_LOW16, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%hi(", 4) == 0) { *strp += 4; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16S, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%uhi(", 5) == 0) { *strp += 5; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_HI16U, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%sdaoff(", 8) == 0) { *strp += 8; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_GPREL, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (strncasecmp (*strp, "%tpoff(", 7) == 0) { *strp += 7; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_MEP_TPREL, &result_type, &value); if (**strp != ')') return "missing `)'"; ++*strp; if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ *valuep = value; return errmsg; } if (**strp == '%') return "invalid %function() here"; errmsg = cgen_parse_address (cd, strp, opindex, BFD_RELOC_NONE, &result_type, &value); if (errmsg == NULL && (result_type != CGEN_PARSE_OPERAND_RESULT_NUMBER || value != 0)) return "not zero"; /* any string will do -- will never be seen. */ return errmsg; } static const char * parse_unsigned7 (CGEN_CPU_DESC cd, const char **strp, enum cgen_operand_type opindex, unsigned long *valuep) { const char *errmsg; bfd_vma value; /* fprintf(stderr, "dj: unsigned7 parse `%s'\n", *strp); */ if (strncasecmp (*strp, "%tpoff(", 7) == 0) { int reloc; *strp += 7; switch (opindex) { case MEP_OPERAND_UDISP7: reloc = BFD_RELOC_MEP_TPREL7; break; case MEP_OPERAND_UDISP7A2: reloc = BFD_RELOC_MEP_TPREL7A2; break; case MEP_OPERAND_UDISP7A4: reloc = BFD_RELOC_MEP_TPREL7A4; break; default: /* Safe assumption? */ abort (); } errmsg = cgen_parse_address (cd, strp, opindex, reloc, NULL, &value); if (**strp != ')') return "missing `)'"; ++*strp; *valuep = value; return errmsg; } if (**strp == '%') return _("invalid %function() here"); return parse_mep_alignu (cd, strp, opindex, valuep); } static ATTRIBUTE_UNUSED const char * parse_cdisp10 (CGEN_CPU_DESC cd, const char **strp, int opindex, long *valuep) { const char *errmsg = 0; signed long value; long have_zero = 0; int wide = 0; int alignment; switch (opindex) { case MEP_OPERAND_CDISP10A4: alignment = 2; break; case MEP_OPERAND_CDISP10A2: alignment = 1; break; case MEP_OPERAND_CDISP10: default: alignment = 0; break; } if ((MEP_CPU & EF_MEP_CPU_MASK) == EF_MEP_CPU_C5) wide = 1; if (strncmp (*strp, "0x0", 3) == 0 || (**strp == '0' && *(*strp + 1) != 'x')) have_zero = 1; errmsg = cgen_parse_signed_integer (cd, strp, opindex, & value); if (errmsg) return errmsg; if (wide) { if (value < -512 || value > 511) return _("Immediate is out of range -512 to 511"); } else { if (value < -128 || value > 127) return _("Immediate is out of range -128 to 127"); } if (value & ((1<>16) & 0xffff)" }, */ /*{ "lo", "(`1 & 0xffff)" }, */ /*{ "sdaoff", "((`1-__sdabase) & 0x7f)"}, */ /*{ "tpoff", "((`1-__tpbase) & 0x7f)"}, */ { 0,0 } }; static char * expand_string (const char *, int); static const char * mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); static char * str_append (char *dest, const char *input, int len) { char *new_dest; int oldlen; if (len == 0) return dest; /* printf("str_append: <<%s>>, <<%s>>, %d\n", dest, input, len); */ oldlen = (dest ? strlen(dest) : 0); new_dest = realloc (dest, oldlen + len + 1); memset (new_dest + oldlen, 0, len + 1); return strncat (new_dest, input, len); } static macro * lookup_macro (const char *name) { macro *m; for (m = macros; m->name; ++m) if (strncmp (m->name, name, strlen(m->name)) == 0) return m; return 0; } static char * expand_macro (arg *args, int narg, macro *mac) { char *result = 0, *rescanned_result = 0; char *e = mac->expansion; char *mark = e; int mac_arg = 0; /* printf("expanding macro %s with %d args\n", mac->name, narg + 1); */ while (*e) { if (*e == '`' && (*e+1) && ((*(e + 1) - '1') <= MAXARGS) && ((*(e + 1) - '1') <= narg)) { result = str_append (result, mark, e - mark); mac_arg = (*(e + 1) - '1'); /* printf("replacing `%d with %s\n", mac_arg+1, args[mac_arg].start); */ result = str_append (result, args[mac_arg].start, args[mac_arg].len); ++e; mark = e+1; } ++e; } if (mark != e) result = str_append (result, mark, e - mark); if (result) { rescanned_result = expand_string (result, 0); free (result); return rescanned_result; } else return result; } #define IN_TEXT 0 #define IN_ARGS 1 static char * expand_string (const char *in, int first_only) { int num_expansions = 0; int depth = 0; int narg = -1; arg args[MAXARGS]; int state = IN_TEXT; const char *mark = in; macro *pmacro = NULL; char *expansion = 0; char *result = 0; while (*in) { switch (state) { case IN_TEXT: if (*in == '%' && *(in + 1) && (!first_only || num_expansions == 0)) { pmacro = lookup_macro (in + 1); if (pmacro) { /* printf("entering state %d at '%s'...\n", state, in); */ result = str_append (result, mark, in - mark); mark = in; in += 1 + strlen (pmacro->name); while (*in == ' ') ++in; if (*in != '(') { state = IN_TEXT; pmacro = NULL; } else { state = IN_ARGS; narg = 0; args[narg].start = in + 1; args[narg].len = 0; mark = in + 1; } } } break; case IN_ARGS: if (depth == 0) { switch (*in) { case ',': narg++; args[narg].start = (in + 1); args[narg].len = 0; break; case ')': state = IN_TEXT; /* printf("entering state %d at '%s'...\n", state, in); */ if (pmacro) { expansion = 0; expansion = expand_macro (args, narg, pmacro); num_expansions++; if (expansion) { result = str_append (result, expansion, strlen (expansion)); free (expansion); } } else { result = str_append (result, mark, in - mark); } pmacro = NULL; mark = in + 1; break; case '(': depth++; default: args[narg].len++; break; } } else { if (*in == ')') depth--; if (narg > -1) args[narg].len++; } } ++in; } if (mark != in) result = str_append (result, mark, in - mark); return result; } #undef IN_ARGS #undef IN_TEXT #undef MAXARGS /* END LIGHTWEIGHT MACRO PROCESSOR. */ const char * mep_cgen_parse_operand (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *); const char * mep_cgen_expand_macros_and_parse_operand (CGEN_CPU_DESC cd, int opindex, const char ** strp_in, CGEN_FIELDS * fields) { const char * errmsg = NULL; char *str = 0, *hold = 0; const char **strp = 0; /* Set up a new pointer to macro-expanded string. */ str = expand_string (*strp_in, 1); /* fprintf (stderr, " expanded <<%s>> to <<%s>>\n", *strp_in, str); */ hold = str; strp = (const char **)(&str); errmsg = mep_cgen_parse_operand (cd, opindex, strp, fields); /* Now work out the advance. */ if (strlen (str) == 0) *strp_in += strlen (*strp_in); else { if (strstr (*strp_in, str)) /* A macro-expansion was pulled off the front. */ *strp_in = strstr (*strp_in, str); else /* A non-macro-expansion was pulled off the front. */ *strp_in += (str - hold); } if (hold) free (hold); return errmsg; } #define CGEN_ASM_INIT_HOOK (cd->parse_operand = mep_cgen_expand_macros_and_parse_operand); /* -- dis.c */ #include "elf/mep.h" #include "elf-bfd.h" #define CGEN_VALIDATE_INSN_SUPPORTED static void print_tpreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); static void print_spreg (CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int); static void print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, unsigned int flags ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "$tp"); } static void print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, PTR dis_info, CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, unsigned int flags ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; (*info->fprintf_func) (info->stream, "$sp"); } /* begin-cop-ip-print-handlers */ static void print_ivc2_cr (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; static void print_ivc2_cr (CGEN_CPU_DESC cd, void *dis_info, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long value, unsigned int attrs) { print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs); } static void print_ivc2_ccr (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; static void print_ivc2_ccr (CGEN_CPU_DESC cd, void *dis_info, CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, long value, unsigned int attrs) { print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs); } /* end-cop-ip-print-handlers */ /************************************************************\ *********************** Experimental ************************* \************************************************************/ #undef CGEN_PRINT_INSN #define CGEN_PRINT_INSN mep_print_insn static int mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, bfd_byte *buf, int corelength, int copro1length, int copro2length ATTRIBUTE_UNUSED) { int i; int status = 0; /* char insnbuf[CGEN_MAX_INSN_SIZE]; */ bfd_byte insnbuf[64]; /* If corelength > 0 then there is a core insn present. It will be at the beginning of the buffer. After printing the core insn, we need to print the + on the next line. */ if (corelength > 0) { int my_status = 0; for (i = 0; i < corelength; i++ ) insnbuf[i] = buf[i]; cd->isas = & MEP_CORE_ISA; my_status = print_insn (cd, pc, info, insnbuf, corelength); if (my_status != corelength) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = corelength; } status += my_status; /* Print the + to indicate that the following copro insn is */ /* part of a vliw group. */ if (copro1length > 0) (*info->fprintf_func) (info->stream, " + "); } /* Now all that is left to be processed is the coprocessor insns In vliw mode, there will always be one. Its positioning will be from byte corelength to byte corelength+copro1length -1. No need to check for existence. Also, the first vliw insn, will, as spec'd, always be at least as long as the core insn so we don't need to flush the buffer. */ if (copro1length > 0) { int my_status = 0; for (i = corelength; i < corelength + copro1length; i++ ) insnbuf[i - corelength] = buf[i]; switch (copro1length) { case 0: break; case 2: cd->isas = & MEP_COP16_ISA; break; case 4: cd->isas = & MEP_COP32_ISA; break; case 6: cd->isas = & MEP_COP48_ISA; break; case 8: cd->isas = & MEP_COP64_ISA; break; default: /* Shouldn't be anything but 16,32,48,64. */ break; } my_status = print_insn (cd, pc, info, insnbuf, copro1length); if (my_status != copro1length) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = copro1length; } status += my_status; } #if 0 /* Now we need to process the second copro insn if it exists. We have no guarantee that the second copro insn will be longer than the first, so we have to flush the buffer if we are have a second copro insn to process. If present, this insn will be in the position from byte corelength+copro1length to byte corelength+copro1length+copro2length-1 (which better equal 8 or else we're in big trouble. */ if (copro2length > 0) { int my_status = 0; for (i = 0; i < 64 ; i++) insnbuf[i] = 0; for (i = corelength + copro1length; i < 64; i++) insnbuf[i - (corelength + copro1length)] = buf[i]; switch (copro2length) { case 2: cd->isas = 1 << ISA_EXT_COP1_16; break; case 4: cd->isas = 1 << ISA_EXT_COP1_32; break; case 6: cd->isas = 1 << ISA_EXT_COP1_48; break; case 8: cd->isas = 1 << ISA_EXT_COP1_64; break; default: /* Shouldn't be anything but 16,32,48,64. */ break; } my_status = print_insn (cd, pc, info, insnbuf, copro2length); if (my_status != copro2length) { (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); my_status = copro2length; } status += my_status; } #endif /* Status should now be the number of bytes that were printed which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */ if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8))) return -1; else return status; } /* The two functions mep_examine_vliw[32,64]_insns are used find out which vliw combinaion (16 bit core with 48 bit copro, 32 bit core with 32 bit copro, etc.) is present. Later on, when internally parallel coprocessors are handled, only these functions should need to be changed. At this time only the following combinations are supported: VLIW32 Mode: 16 bit core insn (core) and 16 bit coprocessor insn (cop1) 32 bit core insn (core) 32 bit coprocessor insn (cop1) Note: As of this time, I do not believe we have enough information to distinguish a 32 bit core insn from a 32 bit cop insn. Also, no 16 bit coprocessor insns have been specified. VLIW64 Mode: 16 bit core insn (core) and 48 bit coprocessor insn (cop1) 32 bit core insn (core) and 32 bit coprocessor insn (cop1) 64 bit coprocessor insn (cop1) The framework for an internally parallel coprocessor is also present (2nd coprocessor insn is cop2), but at this time it is not used. This only appears to be valid in VLIW64 mode. */ static int mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int buflength; int corebuflength; int cop1buflength; int cop2buflength; bfd_byte buf[CGEN_MAX_INSN_SIZE]; char indicator16[1]; char indicatorcop32[2]; /* At this time we're not supporting internally parallel coprocessors, so cop2buflength will always be 0. */ cop2buflength = 0; /* Read in 32 bits. */ buflength = 4; /* VLIW insn spans 4 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } /* Put the big endian representation of the bytes to be examined in the temporary buffers for examination. */ if (info->endian == BFD_ENDIAN_BIG) { indicator16[0] = buf[0]; indicatorcop32[0] = buf[0]; indicatorcop32[1] = buf[1]; } else { indicator16[0] = buf[1]; indicatorcop32[0] = buf[1]; indicatorcop32[1] = buf[0]; } /* If the two high order bits are 00, 01 or 10, we have a 16 bit core insn and a 48 bit copro insn. */ if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) { if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) { /* We have a 32 bit copro insn. */ corebuflength = 0; /* All 4 4ytes are one copro insn. */ cop1buflength = 4; } else { /* We have a 32 bit core. */ corebuflength = 4; cop1buflength = 0; } } else { /* We have a 16 bit core insn and a 16 bit copro insn. */ corebuflength = 2; cop1buflength = 2; } /* Now we have the distrubution set. Print them out. */ status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, cop1buflength, cop2buflength); return status; } static int mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int buflength; int corebuflength; int cop1buflength; int cop2buflength; bfd_byte buf[CGEN_MAX_INSN_SIZE]; char indicator16[1]; char indicator64[4]; /* At this time we're not supporting internally parallel coprocessors, so cop2buflength will always be 0. */ cop2buflength = 0; /* Read in 64 bits. */ buflength = 8; /* VLIW insn spans 8 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } /* We have all 64 bits in the buffer now. We have to figure out what combination of instruction sizes are present. The two high order bits will indicate whether or not we have a 16 bit core insn or not. If not, then we have to look at the 7,8th bytes to tell whether we have 64 bit copro insn or a 32 bit core insn with a 32 bit copro insn. Endianness will make a difference here. */ /* Put the big endian representation of the bytes to be examined in the temporary buffers for examination. */ /* indicator16[0] = buf[0]; */ if (info->endian == BFD_ENDIAN_BIG) { indicator16[0] = buf[0]; indicator64[0] = buf[0]; indicator64[1] = buf[1]; indicator64[2] = buf[2]; indicator64[3] = buf[3]; } else { indicator16[0] = buf[1]; indicator64[0] = buf[1]; indicator64[1] = buf[0]; indicator64[2] = buf[3]; indicator64[3] = buf[2]; } /* If the two high order bits are 00, 01 or 10, we have a 16 bit core insn and a 48 bit copro insn. */ if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) { if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) { /* We have a 64 bit copro insn. */ corebuflength = 0; /* All 8 bytes are one copro insn. */ cop1buflength = 8; } else { /* We have a 32 bit core insn and a 32 bit copro insn. */ corebuflength = 4; cop1buflength = 4; } } else { /* We have a 16 bit core insn and a 48 bit copro insn. */ corebuflength = 2; cop1buflength = 6; } /* Now we have the distrubution set. Print them out. */ status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, cop1buflength, cop2buflength); return status; } #ifdef MEP_IVC2_SUPPORTED static int print_slot_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, SLOTS_ATTR slot, bfd_byte *buf) { const CGEN_INSN_LIST *insn_list; CGEN_INSN_INT insn_value; CGEN_EXTRACT_INFO ex_info; insn_value = cgen_get_insn_value (cd, buf, 32); /* Fill in ex_info fields like read_insn would. Don't actually call read_insn, since the incoming buffer is already read (and possibly modified a la m32r). */ ex_info.valid = (1 << 8) - 1; ex_info.dis_info = info; ex_info.insn_bytes = buf; /* The instructions are stored in hash lists. Pick the first one and keep trying until we find the right one. */ insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); while (insn_list != NULL) { const CGEN_INSN *insn = insn_list->insn; CGEN_FIELDS fields; int length; if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) { insn_list = CGEN_DIS_NEXT_INSN (insn_list); continue; } if ((insn_value & CGEN_INSN_BASE_MASK (insn)) == CGEN_INSN_BASE_VALUE (insn)) { /* Printing is handled in two passes. The first pass parses the machine insn and extracts the fields. The second pass prints them. */ length = CGEN_EXTRACT_FN (cd, insn) (cd, insn, &ex_info, insn_value, &fields, pc); /* Length < 0 -> error. */ if (length < 0) return length; if (length > 0) { CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); /* Length is in bits, result is in bytes. */ return length / 8; } } insn_list = CGEN_DIS_NEXT_INSN (insn_list); } if (slot == SLOTS_P0S) (*info->fprintf_func) (info->stream, "*unknown-p0s*"); else if (slot == SLOTS_P0) (*info->fprintf_func) (info->stream, "*unknown-p0*"); else if (slot == SLOTS_P1) (*info->fprintf_func) (info->stream, "*unknown-p1*"); else if (slot == SLOTS_C3) (*info->fprintf_func) (info->stream, "*unknown-c3*"); return 0; } static int mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED) { int status; int buflength; bfd_byte buf[8]; bfd_byte insn[8]; int e; /* Read in 64 bits. */ buflength = 8; /* VLIW insn spans 8 bytes. */ status = (*info->read_memory_func) (pc, buf, buflength, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } if (info->endian == BFD_ENDIAN_LITTLE) e = 1; else e = 0; if (((unsigned char)buf[0^e] & 0xf0) < 0xc0) { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V1 [-----core-----][--------p0s-------][------------p1------------] */ print_insn (cd, pc, info, buf, 2); insn[0^e] = 0; insn[1^e] = buf[2^e]; insn[2^e] = buf[3^e]; insn[3^e] = buf[4^e] & 0xf0; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P0S, insn); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07) { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */ /* 00000000111111112222222233333333 */ insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4; insn[1^e] = buf[2^e]; insn[2^e] = buf[3^e]; insn[3^e] = buf[4^e] & 0xf0; print_slot_insn (cd, pc, info, SLOTS_P0, insn); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } else { /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ /* V2 [-------------core-------------]xxxx[------------p1------------] */ print_insn (cd, pc, info, buf, 4); insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; insn[3^e] = buf[7^e] << 4; (*info->fprintf_func) (info->stream, " + "); print_slot_insn (cd, pc, info, SLOTS_P1, insn); } return 8; } #endif /* MEP_IVC2_SUPPORTED */ /* This is a hack. SID calls this to update the disassembler as the CPU changes modes. */ static int mep_ivc2_disassemble_p = 0; static int mep_ivc2_vliw_disassemble_p = 0; void mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx); void mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx) { mep_ivc2_disassemble_p = ivc2_p; mep_ivc2_vliw_disassemble_p = vliw_p; mep_config_index = cfg_idx; } static int mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { int status; int cop_type; int ivc2 = 0; static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL; if (ivc2_core_isa == NULL) { /* IVC2 has some core-only coprocessor instructions. We use COP32 to flag those, and COP64 for the VLIW ones, since they have the same names. */ ivc2_core_isa = cgen_bitset_create (MAX_ISAS); } /* Extract and adapt to configuration number, if available. */ if (info->section && info->section->owner) { bfd *abfd = info->section->owner; mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; if (cop_type == EF_MEP_COP_IVC2) ivc2 = 1; } /* Picking the right ISA bitmask for the current context is tricky. */ if (info->section) { if (info->section->flags & SEC_MEP_VLIW) { #ifdef MEP_IVC2_SUPPORTED if (ivc2) { /* ivc2 has its own way of selecting its functions. */ cd->isas = & MEP_CORE_ISA; status = mep_examine_ivc2_insns (cd, pc, info); } else #endif /* Are we in 32 or 64 bit vliw mode? */ if (MEP_VLIW64) status = mep_examine_vliw64_insns (cd, pc, info); else status = mep_examine_vliw32_insns (cd, pc, info); /* Both the above branches set their own isa bitmasks. */ } else { if (ivc2) { cgen_bitset_clear (ivc2_core_isa); cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa); cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa); cd->isas = ivc2_core_isa; } else cd->isas = & MEP_CORE_ISA; status = default_print_insn (cd, pc, info); } } else /* sid or gdb */ { #ifdef MEP_IVC2_SUPPORTED if (mep_ivc2_disassemble_p) { if (mep_ivc2_vliw_disassemble_p) { cd->isas = & MEP_CORE_ISA; status = mep_examine_ivc2_insns (cd, pc, info); return status; } else { if (ivc2) cd->isas = ivc2_core_isa; } } #endif status = default_print_insn (cd, pc, info); } return status; } /* -- opc.c */ #include "elf/mep.h" /* A mask for all ISAs executed by the core. */ CGEN_ATTR_VALUE_BITSET_TYPE mep_all_core_isas_mask = {0, 0}; void init_mep_all_core_isas_mask (void) { if (mep_all_core_isas_mask.length != 0) return; cgen_bitset_init (& mep_all_core_isas_mask, ISA_MAX); cgen_bitset_set (& mep_all_core_isas_mask, ISA_MEP); /* begin-all-core-isas */ cgen_bitset_add (& mep_all_core_isas_mask, ISA_EXT_CORE1); /* end-all-core-isas */ } CGEN_ATTR_VALUE_BITSET_TYPE mep_all_cop_isas_mask = {0, 0}; void init_mep_all_cop_isas_mask (void) { if (mep_all_cop_isas_mask.length != 0) return; cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX); /* begin-all-cop-isas */ cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_16); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_32); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_48); cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_64); /* end-all-cop-isas */ } int mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *isa_mask) { CGEN_BITSET insn_isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); return cgen_bitset_intersect_p (& insn_isas, isa_mask); } #define OPTION_MASK \ ( (1 << CGEN_INSN_OPTIONAL_BIT_INSN) \ | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DEBUG_INSN) \ | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) \ | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) \ | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) \ | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) \ | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) \ | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CP_INSN) \ | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) ) mep_config_map_struct mep_config_map[] = { /* config-map-start */ /* Default entry: first module, with all options enabled. */ { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, 0 | (1 << CGEN_INSN_OPTIONAL_CP_INSN) | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) | (1 << CGEN_INSN_OPTIONAL_BIT_INSN) | (1 << CGEN_INSN_OPTIONAL_LDZ_INSN) | (1 << CGEN_INSN_OPTIONAL_ABS_INSN) | (1 << CGEN_INSN_OPTIONAL_AVE_INSN) | (1 << CGEN_INSN_OPTIONAL_MINMAX_INSN) | (1 << CGEN_INSN_OPTIONAL_CLIP_INSN) | (1 << CGEN_INSN_OPTIONAL_SAT_INSN) }, /* config-map-end */ { 0, 0, 0, 0, 0, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0}, 0 } }; int mep_config_index = 0; static int check_configured_mach (int machs) { /* All base insns are supported. */ int mach = 1 << MACH_BASE; switch (MEP_CPU & EF_MEP_CPU_MASK) { case EF_MEP_CPU_C2: case EF_MEP_CPU_C3: mach |= (1 << MACH_MEP); break; case EF_MEP_CPU_H1: mach |= (1 << MACH_H1); break; case EF_MEP_CPU_C5: mach |= (1 << MACH_MEP); mach |= (1 << MACH_C5); break; default: break; } return machs & mach; } int mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int iconfig = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG); int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); int ok1; int ok2; int ok3; /* If the insn has an option bit set that we don't want, reject it. */ if (CGEN_INSN_ATTRS (insn)->bool_ & OPTION_MASK & ~MEP_OMASK) return 0; /* If attributes are absent, assume no restriction. */ if (machs == 0) machs = ~0; ok1 = ((machs & cd->machs) && cgen_bitset_intersect_p (& isas, cd->isas)); /* If the insn is config-specific, make sure it matches. */ ok2 = (iconfig == 0 || iconfig == MEP_CONFIG); /* Make sure the insn is supported by the configured mach */ ok3 = check_configured_mach (machs); return (ok1 && ok2 && ok3); } int mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { #ifdef MEP_IVC2_SUPPORTED /* If we're assembling VLIW packets, ignore the 12-bit BSR as we can't relax that. The 24-bit BSR is matched instead. */ if (insn->base->num == MEP_INSN_BSR12 && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64)) return 0; #endif return mep_cgen_insn_supported (cd, insn); } @