head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC6:1.1.1.1 netbsd-11-0-RC5:1.1.1.1 netbsd-11-0-RC4:1.1.1.1 netbsd-11-0-RC3:1.1.1.1 gdb-17-1:1.1.1.1 netbsd-11-0-RC2:1.1.1.1 netbsd-11-0-RC1:1.1.1.1 gdb-16-3:1.1.1.1 perseant-exfatfs-base-20250801:1.1.1.1 netbsd-11:1.1.1.1.0.44 netbsd-11-base:1.1.1.1 netbsd-10-1-RELEASE:1.1.1.1 gdb-15-1:1.1.1.1 perseant-exfatfs-base-20240630:1.1.1.1 perseant-exfatfs:1.1.1.1.0.42 perseant-exfatfs-base:1.1.1.1 netbsd-8-3-RELEASE:1.1.1.1 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.1 netbsd-10-0-RC6:1.1.1.1 netbsd-10-0-RC5:1.1.1.1 netbsd-10-0-RC4:1.1.1.1 netbsd-10-0-RC3:1.1.1.1 netbsd-10-0-RC2:1.1.1.1 netbsd-10-0-RC1:1.1.1.1 gdb-13-2:1.1.1.1 netbsd-10:1.1.1.1.0.40 netbsd-10-base:1.1.1.1 netbsd-9-3-RELEASE:1.1.1.1 cjep_sun2x-base1:1.1.1.1 cjep_sun2x:1.1.1.1.0.38 cjep_sun2x-base:1.1.1.1 cjep_staticlib_x-base1:1.1.1.1 netbsd-9-2-RELEASE:1.1.1.1 cjep_staticlib_x:1.1.1.1.0.36 cjep_staticlib_x-base:1.1.1.1 netbsd-9-1-RELEASE:1.1.1.1 GDB-11-0-50-20200914-git:1.1.1.1 phil-wifi-20200421:1.1.1.1 phil-wifi-20200411:1.1.1.1 is-mlppp:1.1.1.1.0.34 is-mlppp-base:1.1.1.1 phil-wifi-20200406:1.1.1.1 netbsd-8-2-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 phil-wifi-20191119:1.1.1.1 netbsd-9:1.1.1.1.0.32 netbsd-9-base:1.1.1.1 phil-wifi-20190609:1.1.1.1 netbsd-8-1-RELEASE:1.1.1.1 gdb-8-3:1.1.1.1 netbsd-8-1-RC1:1.1.1.1 pgoyette-compat-merge-20190127:1.1.1.1 pgoyette-compat-20190127:1.1.1.1 pgoyette-compat-20190118:1.1.1.1 pgoyette-compat-1226:1.1.1.1 pgoyette-compat-1126:1.1.1.1 pgoyette-compat-1020:1.1.1.1 pgoyette-compat-0930:1.1.1.1 pgoyette-compat-0906:1.1.1.1 netbsd-7-2-RELEASE:1.1.1.1 pgoyette-compat-0728:1.1.1.1 netbsd-8-0-RELEASE:1.1.1.1 phil-wifi:1.1.1.1.0.30 phil-wifi-base:1.1.1.1 pgoyette-compat-0625:1.1.1.1 netbsd-8-0-RC2:1.1.1.1 pgoyette-compat-0521:1.1.1.1 pgoyette-compat-0502:1.1.1.1 pgoyette-compat-0422:1.1.1.1 netbsd-8-0-RC1:1.1.1.1 pgoyette-compat-0415:1.1.1.1 pgoyette-compat-0407:1.1.1.1 pgoyette-compat-0330:1.1.1.1 pgoyette-compat-0322:1.1.1.1 pgoyette-compat-0315:1.1.1.1 netbsd-7-1-2-RELEASE:1.1.1.1 pgoyette-compat:1.1.1.1.0.28 pgoyette-compat-base:1.1.1.1 netbsd-7-1-1-RELEASE:1.1.1.1 gdb-8-0-1:1.1.1.1 matt-nb8-mediatek:1.1.1.1.0.26 matt-nb8-mediatek-base:1.1.1.1 perseant-stdc-iso10646:1.1.1.1.0.24 perseant-stdc-iso10646-base:1.1.1.1 netbsd-8:1.1.1.1.0.22 netbsd-8-base:1.1.1.1 prg-localcount2-base3:1.1.1.1 prg-localcount2-base2:1.1.1.1 prg-localcount2-base1:1.1.1.1 prg-localcount2:1.1.1.1.0.20 prg-localcount2-base:1.1.1.1 pgoyette-localcount-20170426:1.1.1.1 bouyer-socketcan-base1:1.1.1.1 pgoyette-localcount-20170320:1.1.1.1 netbsd-7-1:1.1.1.1.0.18 netbsd-7-1-RELEASE:1.1.1.1 netbsd-7-1-RC2:1.1.1.1 netbsd-7-nhusb-base-20170116:1.1.1.1 bouyer-socketcan:1.1.1.1.0.16 bouyer-socketcan-base:1.1.1.1 pgoyette-localcount-20170107:1.1.1.1 netbsd-7-1-RC1:1.1.1.1 pgoyette-localcount-20161104:1.1.1.1 netbsd-7-0-2-RELEASE:1.1.1.1 gdb-7-12:1.1.1.1 localcount-20160914:1.1.1.1 netbsd-7-nhusb:1.1.1.1.0.14 netbsd-7-nhusb-base:1.1.1.1 pgoyette-localcount-20160806:1.1.1.1 pgoyette-localcount-20160726:1.1.1.1 pgoyette-localcount:1.1.1.1.0.12 pgoyette-localcount-base:1.1.1.1 netbsd-7-0-1-RELEASE:1.1.1.1 gdb-7-10-1:1.1.1.1 netbsd-7-0:1.1.1.1.0.10 netbsd-7-0-RELEASE:1.1.1.1 gdb-7-9-1:1.1.1.1 netbsd-7-0-RC3:1.1.1.1 netbsd-7-0-RC2:1.1.1.1 netbsd-7-0-RC1:1.1.1.1 tls-maxphys-base:1.1.1.1 tls-maxphys:1.1.1.1.0.8 netbsd-7:1.1.1.1.0.6 netbsd-7-base:1.1.1.1 gdb-7-7-1:1.1.1.1 yamt-pagecache:1.1.1.1.0.4 yamt-pagecache-base9:1.1.1.1 tls-earlyentropy:1.1.1.1.0.2 tls-earlyentropy-base:1.1.1.1 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.1 riastradh-drm2-base3:1.1.1.1 gdb-7-6-1:1.1.1.1 FSF:1.1.1; locks; strict; comment @# @; 1.1 date 2013.10.03.15.44.15; author christos; state Exp; branches 1.1.1.1; next ; commitid m91IYDmHTME7wR7x; 1.1.1.1 date 2013.10.03.15.44.15; author christos; state Exp; branches 1.1.1.1.4.1 1.1.1.1.8.1; next ; commitid m91IYDmHTME7wR7x; 1.1.1.1.4.1 date 2013.10.03.15.44.15; author yamt; state dead; branches; next 1.1.1.1.4.2; commitid SRuOnF9k1i4dcyBx; 1.1.1.1.4.2 date 2014.05.22.16.00.32; author yamt; state Exp; branches; next ; commitid SRuOnF9k1i4dcyBx; 1.1.1.1.8.1 date 2013.10.03.15.44.15; author tls; state dead; branches; next 1.1.1.1.8.2; commitid jTnpym9Qu0o4R1Nx; 1.1.1.1.8.2 date 2014.08.19.23.58.39; author tls; state Exp; branches; next ; commitid jTnpym9Qu0o4R1Nx; desc @@ 1.1 log @Initial revision @ text @; Copyright 2011 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; ; ; This file is part of the GNU Binutils. ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ; MA 02110-1301, USA. ;; This coprocessor definition is being used to verify vliw mode behaviour. ;; This is a mock-up done by Red Hat and is in no way supposed to represent ;; a real coprocessor. The hardware is defined in mep-core.cpu. ; Coprocessor registers (define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) (define-hardware (name h-cr64-rh-1) (comment "64-bit coprocessor registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register DI (32)) (set (index newval) (c-call VOID "h_cr64_set" index newval)) (get (index) (c-call DI "h_cr64_get" index)) (indices keyword "$c" (.map -reg-pair (.iota 32))) ) (define-hardware (name h-cr-rh-1) (comment "32-bit coprocessor registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register SI (32)) (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) (get (index) (trunc SI (c-call DI "h_cr64_get" index))) (indices keyword "$c" (.map -reg-pair (.iota 32))) ) (define-hardware (name h-ccr-rh-1) (comment "Coprocessor control registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register SI (64)) (set (index newval) (c-call VOID "h_ccr_set" index newval)) (get (index) (c-call DI "h_ccr_get" index)) (indices keyword "" (.map -ccr-reg-pair (.iota 64))) ) ; ifields For 16-bit insns (dnf f-cphigh4 "High 4 bits" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 0 4) (dnf f-cpcrn "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 4 5) (dnf f-cpcrm "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 11 5) (dnf f-uu2 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 2) (dnf f-uu3 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 3) (dnf f-cprm "Core GPR" ((ISA ext_cop1_16)) 12 4) ; ifields For 32-bit insns (some of the above are used too) ; Notes: ; ; f-alone: A value of 0111 means that the insn can run alone in ; one of the vliw modes. ; ; f-seg32: Together f-seg32 and f-seg32-a allow 64 different 32-bit ; f-seg32-a: insns to be defined. (dnf f-seg32 "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 9 3) (dnf f-alone "Run-alone indicator" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64)) 12 4) (dnf f-seg32-a "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 21 3) (dnf f-code8 "8 bit unsigned immediate" ((ISA ext_cop1_32)) 24 8) (dnf f-cpcrm-32 "Corpocessor Reg" ((ISA ext_cop1_32)) 16 5) ; ifields for 48-bit insns ; Note: Part of f-uu12 can be broken off later to enumerate ; any 48-bit insns that may be added. (dnf f-uu12 "Unusued 12 bits" ((ISA ext_cop1_48)) 4 12) (dnf f-code16a "Unsigned immediate" ((ISA ext_cop1_48)) 16 16) (dnf f-code16b "Unsigned immediate" ((ISA ext_cop1_48,ext_cop1_64)) 32 16) ; ifields for 64-bit insns (dnf f-uu8 "Unsused 8 bits" ((ISA ext_cop1_64)) 4 8) (dnf f-uu8a "Unused 13 bits" ((ISA ext_cop1_64)) 16 8) (dnf f-seg64 "Enumerate 64-bit insns" ((ISA ext_cop1_64)) 24 8) (dnf f-code16c "Unsigned immediate" ((ISA ext_cop1_64)) 48 16) (dnf f-cpcrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 5) (dnf f-cpcrm-64 "Coprocessor Register" ((ISA ext_cop1_64)) 37 4) (dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 41 23) (dnf f-cpccrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 4) (dnf f-cpccrm-64 "Core GPR" ((ISA ext_cop1_64)) 36 4) (dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 40 24) ; Operands for 16-bit insns (dnop cpcrn "cpcrn" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn) (dnop cpcrm "cpcrm" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm) (dnop cprm "cprm" ((ISA ext_cop1_16)) h-gpr f-cprm) ; Additional operands for 32-bit insns (dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8) ; Operands for 48-bit insns (dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a) (dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b) ; Additional operands for 64-bit insns (dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c) (dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64) (dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64) (dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64) (dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64) (dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23) (dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24) ; 16- and 32-bit nops can be defined as normal instructions without ; any problems. nops take no operands, so nops longer than 32 ; bits cannot be defined as normal insns since that would result in ; decodable bits beyond cgen's 32-bit boundary. As a result, we ; have to use macros and other real insns to create 48- and 64-bit nops. ; ; In addition, since the names of the nops that will be created as part ; of future insn sets are not known at this time, the assembler needs a ; fixed set of nop names that it can use for automatic nop insertion. ; The idea is that no matter what those insns are called, we don't want ; to have to change the C code in the assemblers vliw grouping validation ; and nop insertion routines. We therefore have to create macros for ; all nops to map the macro names which are known to the assembler to the ; names of the real nop insns. ; ; These emitted insns in these macros will need to be modified when ; new nops are defined in new coprocessor insn sets. ; A real 16-bit nop insn exists (dnmi cpnop16 "cpnop16" ((ISA ext_cop1_16)) "cpnop16" (emit cp16nop) ) ; A real 32-bit nop insn exists (dnmi cpnop32 "cpnop32" ((ISA ext_cop1_32)) "cpnop32" (emit cp32nop) ) ; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop. (dnmi cpnop48 "cpnop48" ((ISA ext_cop1_48)) "cpnop48" (emit cpf1nop (code16a 0) (code16b 0)) ) ; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop. (dnmi cpnop64 "cpnop64" ((ISA ext_cop1_64)) "cpnop64" (emit cpf3nop (code16b 0) (code16c 0)) ) (define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16)) (define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32)) (define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48)) (define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64)) ; 16-Bit Insns (dncp116i movcp16 "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16 $cpcrn,$cpcrm" (+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm) (set cpcrn cpcrm) () ) (dncp116i movcp16a "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16a $cpcrn,$cprm" (+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm) (set cpcrn (zext DI cprm)) () ) (dncp116i movcp16b "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16b $cprm,$cpcrn" (+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm) (set cprm (subword SI cpcrn 1)) () ) (dncp116i cp16nop "16-bit coprocessor nop" (VLIW64_NO_MATCHING_NOP) "cp16nop" (+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0)) (unimp "cp16nop") () ) ; 32-Bit Insns (dncp132i cp32nop "32-bit coprocessor nop" (VLIW64_NO_MATCHING_NOP) "cp32nop" (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) (f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0)) (unimp "cpnop32") () ) (dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests " (VLIW64_NO_MATCHING_NOP) "cpf2 $code8" (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) (f-cpcrm-32 0) (f-seg32-a 1) code8) (unimp "cpf2") () ) ; 48-Bit Insns (dncp148i cpf1 "48-bit coprocessor helper insn" () "cpf1 $code16a,$code16b" (+ (f-cphigh4 4) (f-uu12 0) code16a code16b) (sequence ((HI result)) (if (eq code16a 0) (set pc (c-call USI "cop_exception" pc)) ; Set branch condition flags to value of code16a[0:3] ; Branch condition flags do not exist yet. (nop) ) ) () ) (dncp148i cpf1nop "48-bit coprocessor nop insn" () "cpf1nop $code16a,$code16b" (+ (f-cphigh4 5) (f-uu12 0) code16a code16b) (sequence ((HI result)) (set result (add code16a code16b)) ) () ) ; 64-Bit Insns (dncp164i cpf3 "64-bit coprocessor helper insn" () "cpf3 $code16b,$code16c" (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 0) code16b code16c) (sequence ((HI result)) (set result (add code16b code16c)) ) () ) (dncp164i cpf3nop "64-bit coprocessor helper insn" () "cpf3nop $code16b,$code16c" (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 7) code16b code16c) (sequence ((HI result)) (set result (add code16b code16c)) ) () ) (dncp164i cmov64a "64-bit cmov" () "cmov64a $cpcrn64,$cpcrm64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 1) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrn64 (zext DI cpcrm64))) () ) (dncp164i cmov64b "64-bit cmov" () "cmov64b $cpcrm64,$cpcrn64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 2) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrm64 (subword SI cpcrn64 1))) () ) (dncp164i cmovh64a "64-bit cmovh" () "cmovh64a $cpcrn64,$cpcrm64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 3) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1))))) () ) (dncp164i cmovh64b "64-bit cmovh" () "cmovh64b $cpcrm64,$cpcrn64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 4) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrm64 (subword SI cpcrn64 0))) () ) (dncp164i cmovc64a "64-bit cmovc" () "cmovc64a $cpccrn64,$cpccrm64,$cpcode24" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 5) cpccrn64 cpccrm64 cpcode24) (sequence ((SI dummy)) (set dummy cpcode24) (set cpccrn64 cpccrm64)) () ) (dncp164i cmovc64b "64-bit cmovc" () "cmovc64b $cpccrm64,$cpccrn64,$cpcode24" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 6) cpccrn64 cpccrm64 cpcode24) (sequence ((SI dummy)) (set dummy cpcode24) (set cpccrm64 cpccrn64)) () ) @ 1.1.1.1 log @Import gdb 7.6.1 News from: http://sourceware.org/gdb/news: August 30th, 2013: GDB 7.6.1 Released! The latest version of GDB, version 7.6.1, is available for download. This is a minor corrective release over GDB 7.6, fixing the following issues: PR tdep/15420 (Cannot debug threaded programs on newer versions of x86-solaris - Solaris 10, Update 10 or later) PR remote/15455 (QTro remote packet broken) PR build/15476 (Build failure due to incomplete enum type in utils.h) PR server/15594 (tls support in 64x32 x86 gdbserver doesn't extend address to 64 bit) PR server/15075 (dprintf inteferes with "next") PR server/15434 (dprintf uses a synchronous 'continue' even in non-stop mode) PR tui/14880 (In split register layouts, up results in assertion failure in value.c) PR c++/15519 (GDB 7.6 is 94x slower than GDB 7.5.1 using a certain core file) PR gdb/15837 (GDB prints entry values for local variables) PR gdb/15415 (gdb resolves symbolic links when passing argv[0]) PR cli/15603 (CTRL-C can no longer interrupt inferior) PR gdb/15604 (gdbserver socket leak 7.5 regression) April 26th, 2013: GDB 7.6 Released! The latest version of GDB, version 7.6, is available for download. Changes in this release include: New native configurations (ARM AArch64 GNU/Linux, FreeBSD/powerpc, 86_64/Cygwin and Tilera TILE-Gx GNU/Linux) New target configurations (ARM AArch64, ARM AArch64 GNU/Linux, Lynx 178 PowerPC, x86_64/Cygwin, and Tilera TILE-Gx GNU/Linux) Support for the "mini debuginfo" section, .gnu_debugdata The C++ ABI now defaults to the GNU v3 ABI More Python scripting improvements Some GDB/MI improvements New configure options, new commands, and options New remote packets A new "target record-btrace" has been added while the "target record" command has been renamed to "target record-full" See the NEWS file for a more complete and detailed list of what this release includes. March 12th, 2013: GDB 7.6 branch created The GDB 7.6 branch (gdb_7_6-branch) has been created. To check out a copy of the branch use: cvs -d :pserver:anoncvs@@sourceware.org:/cvs/src co -r gdb_7_6-branch gdb November 29th, 2012: GDB 7.5.1 Released! The latest version of GDB, version 7.5.1, is available for download. This is a minor corrective release over GDB 7.5, fixing the following issues: An "Attempt to dereference a generic pointer" errors (-var-create). Backtrace problems on x32 (PR backtrace/14646). next/step/finish problems on x32 (PR gdb/14647). A "malformed linespec error: unexpected keyword, [...]" error (PR breakpoints/14643). GDB crash while stepping through powerpc (32bits) code. A failed assertion in linux_ptrace_test_ret_to_nx. A "!frame_id_inlined_p (frame_id)" failed assertion. A "No more reverse-execution history." error during reverse "next" execution (PR 14548). Incomplete command descriptions in "apropos" output. PR gdb/14494 (a GDB crash difficult to characterize). Various build warnings. August 17th, 2012: GDB 7.5 Released! The latest version of GDB, version 7.5, is available for download. Changes in this release include: Go language support. New targets (x32 ABI, microMIPS, Renesas RL78, HP OpenVMS ia64). More Python scripting improvements. SDT (Static Defined Tracing) probes support with SystemTap probes. GDBserver improvements (stdio connections, target-side evaluation of breakpoint conditions, remote protocol improvements). Other miscellaneous improvements (ability to stop when a shared library is loaded/unloaded, dynamic printf, etc). Reverse debugging on ARM. The binary "gdbtui" has been abandoned and can no longer be built. Use "gdb -tui" instead. See the NEWS file for a more complete and detailed list of what this release includes. July 17th, 2012: GDB 7.5 branch created The GDB 7.5 branch (gdb_7_5-branch) has been created. To check out a copy of the branch use: cvs -d :pserver:anoncvs@@sourceware.org:/cvs/src co -r gdb_7_5-branch gdb April 26th, 2012: GDB 7.4.1 Released! The latest version of GDB, version 7.4.1, is available for download. This is a minor corrective release over GDB 7.4, fixing the following issues: [GDB/MI] Error when resuming program execution in all-stop mode ("Cannot execute this command without a live selected thread"). [Pascal] Polluted display of class methods parameters. [target remote] Errror when connecting to remote target where disconnected tracing is in effect. [AVX] Float and ymm* register values not available. [GDB] Crash when using the "finish" command. [build] makeinfo should not be required to build GDB. January 24th, 2012: GDB 7.4 Released! The latest version of GDB, version 7.4, is available for download. Changes in this release include: Many Python scripting improvements Better support for ambiguous linespecs Masked watchpoints Tracepoint support improvements Support for Texas Instruments TMS320C6x (tic6x-*-*) A Renesas RL78 simulator (rl78-*-elf) Some minor Remote protocol extensions and GDB/MI changes See the NEWS file for a more complete and detailed list of what this release includes. Note that the gdbtui binary is deprecated, starting with GDB 7.5. Use "gdb -tui" instead. January 9, 2012: Extensibility support using Guile GDB ought to support extensibility using Guile, the GNU extensibility package (an implementation of Scheme). We are looking for people to write the code to interface the two. Please write to gdb-patches AT sourceware DOT org if you are interested. December 13, 2011: GDB 7.4 branch created The GDB 7.4 branch (gdb_7_4-branch) has been created. To check out a copy of the branch use: cvs -d :pserver:anoncvs@@sourceware.org:/cvs/src co -r gdb_7_4-branch gdb September 30, 2011: Release Mistakes in GDB Versions 6.0 - 7.3 A mistake has been detected in the release tar files for all GDB releases from version 6.0 to version 7.3 (included). The mistake has been corrected, and the FSF issued the following announcements: Making up for a release mistake in GDB versions 6.0 - 6.6 Making up for a release mistake in GDB versions 6.7 - 7.3 @ text @@ 1.1.1.1.8.1 log @file mep-rhcop.cpu was added on branch tls-maxphys on 2014-08-19 23:58:39 +0000 @ text @d1 342 @ 1.1.1.1.8.2 log @Rebase to HEAD as of a few days ago. @ text @a0 342 ; Copyright 2011 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; ; ; This file is part of the GNU Binutils. ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ; MA 02110-1301, USA. ;; This coprocessor definition is being used to verify vliw mode behaviour. ;; This is a mock-up done by Red Hat and is in no way supposed to represent ;; a real coprocessor. The hardware is defined in mep-core.cpu. ; Coprocessor registers (define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) (define-hardware (name h-cr64-rh-1) (comment "64-bit coprocessor registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register DI (32)) (set (index newval) (c-call VOID "h_cr64_set" index newval)) (get (index) (c-call DI "h_cr64_get" index)) (indices keyword "$c" (.map -reg-pair (.iota 32))) ) (define-hardware (name h-cr-rh-1) (comment "32-bit coprocessor registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register SI (32)) (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) (get (index) (trunc SI (c-call DI "h_cr64_get" index))) (indices keyword "$c" (.map -reg-pair (.iota 32))) ) (define-hardware (name h-ccr-rh-1) (comment "Coprocessor control registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register SI (64)) (set (index newval) (c-call VOID "h_ccr_set" index newval)) (get (index) (c-call DI "h_ccr_get" index)) (indices keyword "" (.map -ccr-reg-pair (.iota 64))) ) ; ifields For 16-bit insns (dnf f-cphigh4 "High 4 bits" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 0 4) (dnf f-cpcrn "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 4 5) (dnf f-cpcrm "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 11 5) (dnf f-uu2 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 2) (dnf f-uu3 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 3) (dnf f-cprm "Core GPR" ((ISA ext_cop1_16)) 12 4) ; ifields For 32-bit insns (some of the above are used too) ; Notes: ; ; f-alone: A value of 0111 means that the insn can run alone in ; one of the vliw modes. ; ; f-seg32: Together f-seg32 and f-seg32-a allow 64 different 32-bit ; f-seg32-a: insns to be defined. (dnf f-seg32 "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 9 3) (dnf f-alone "Run-alone indicator" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64)) 12 4) (dnf f-seg32-a "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 21 3) (dnf f-code8 "8 bit unsigned immediate" ((ISA ext_cop1_32)) 24 8) (dnf f-cpcrm-32 "Corpocessor Reg" ((ISA ext_cop1_32)) 16 5) ; ifields for 48-bit insns ; Note: Part of f-uu12 can be broken off later to enumerate ; any 48-bit insns that may be added. (dnf f-uu12 "Unusued 12 bits" ((ISA ext_cop1_48)) 4 12) (dnf f-code16a "Unsigned immediate" ((ISA ext_cop1_48)) 16 16) (dnf f-code16b "Unsigned immediate" ((ISA ext_cop1_48,ext_cop1_64)) 32 16) ; ifields for 64-bit insns (dnf f-uu8 "Unsused 8 bits" ((ISA ext_cop1_64)) 4 8) (dnf f-uu8a "Unused 13 bits" ((ISA ext_cop1_64)) 16 8) (dnf f-seg64 "Enumerate 64-bit insns" ((ISA ext_cop1_64)) 24 8) (dnf f-code16c "Unsigned immediate" ((ISA ext_cop1_64)) 48 16) (dnf f-cpcrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 5) (dnf f-cpcrm-64 "Coprocessor Register" ((ISA ext_cop1_64)) 37 4) (dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 41 23) (dnf f-cpccrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 4) (dnf f-cpccrm-64 "Core GPR" ((ISA ext_cop1_64)) 36 4) (dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 40 24) ; Operands for 16-bit insns (dnop cpcrn "cpcrn" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn) (dnop cpcrm "cpcrm" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm) (dnop cprm "cprm" ((ISA ext_cop1_16)) h-gpr f-cprm) ; Additional operands for 32-bit insns (dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8) ; Operands for 48-bit insns (dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a) (dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b) ; Additional operands for 64-bit insns (dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c) (dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64) (dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64) (dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64) (dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64) (dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23) (dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24) ; 16- and 32-bit nops can be defined as normal instructions without ; any problems. nops take no operands, so nops longer than 32 ; bits cannot be defined as normal insns since that would result in ; decodable bits beyond cgen's 32-bit boundary. As a result, we ; have to use macros and other real insns to create 48- and 64-bit nops. ; ; In addition, since the names of the nops that will be created as part ; of future insn sets are not known at this time, the assembler needs a ; fixed set of nop names that it can use for automatic nop insertion. ; The idea is that no matter what those insns are called, we don't want ; to have to change the C code in the assemblers vliw grouping validation ; and nop insertion routines. We therefore have to create macros for ; all nops to map the macro names which are known to the assembler to the ; names of the real nop insns. ; ; These emitted insns in these macros will need to be modified when ; new nops are defined in new coprocessor insn sets. ; A real 16-bit nop insn exists (dnmi cpnop16 "cpnop16" ((ISA ext_cop1_16)) "cpnop16" (emit cp16nop) ) ; A real 32-bit nop insn exists (dnmi cpnop32 "cpnop32" ((ISA ext_cop1_32)) "cpnop32" (emit cp32nop) ) ; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop. (dnmi cpnop48 "cpnop48" ((ISA ext_cop1_48)) "cpnop48" (emit cpf1nop (code16a 0) (code16b 0)) ) ; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop. (dnmi cpnop64 "cpnop64" ((ISA ext_cop1_64)) "cpnop64" (emit cpf3nop (code16b 0) (code16c 0)) ) (define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16)) (define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32)) (define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48)) (define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64)) ; 16-Bit Insns (dncp116i movcp16 "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16 $cpcrn,$cpcrm" (+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm) (set cpcrn cpcrm) () ) (dncp116i movcp16a "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16a $cpcrn,$cprm" (+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm) (set cpcrn (zext DI cprm)) () ) (dncp116i movcp16b "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16b $cprm,$cpcrn" (+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm) (set cprm (subword SI cpcrn 1)) () ) (dncp116i cp16nop "16-bit coprocessor nop" (VLIW64_NO_MATCHING_NOP) "cp16nop" (+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0)) (unimp "cp16nop") () ) ; 32-Bit Insns (dncp132i cp32nop "32-bit coprocessor nop" (VLIW64_NO_MATCHING_NOP) "cp32nop" (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) (f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0)) (unimp "cpnop32") () ) (dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests " (VLIW64_NO_MATCHING_NOP) "cpf2 $code8" (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) (f-cpcrm-32 0) (f-seg32-a 1) code8) (unimp "cpf2") () ) ; 48-Bit Insns (dncp148i cpf1 "48-bit coprocessor helper insn" () "cpf1 $code16a,$code16b" (+ (f-cphigh4 4) (f-uu12 0) code16a code16b) (sequence ((HI result)) (if (eq code16a 0) (set pc (c-call USI "cop_exception" pc)) ; Set branch condition flags to value of code16a[0:3] ; Branch condition flags do not exist yet. (nop) ) ) () ) (dncp148i cpf1nop "48-bit coprocessor nop insn" () "cpf1nop $code16a,$code16b" (+ (f-cphigh4 5) (f-uu12 0) code16a code16b) (sequence ((HI result)) (set result (add code16a code16b)) ) () ) ; 64-Bit Insns (dncp164i cpf3 "64-bit coprocessor helper insn" () "cpf3 $code16b,$code16c" (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 0) code16b code16c) (sequence ((HI result)) (set result (add code16b code16c)) ) () ) (dncp164i cpf3nop "64-bit coprocessor helper insn" () "cpf3nop $code16b,$code16c" (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 7) code16b code16c) (sequence ((HI result)) (set result (add code16b code16c)) ) () ) (dncp164i cmov64a "64-bit cmov" () "cmov64a $cpcrn64,$cpcrm64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 1) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrn64 (zext DI cpcrm64))) () ) (dncp164i cmov64b "64-bit cmov" () "cmov64b $cpcrm64,$cpcrn64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 2) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrm64 (subword SI cpcrn64 1))) () ) (dncp164i cmovh64a "64-bit cmovh" () "cmovh64a $cpcrn64,$cpcrm64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 3) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1))))) () ) (dncp164i cmovh64b "64-bit cmovh" () "cmovh64b $cpcrm64,$cpcrn64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 4) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrm64 (subword SI cpcrn64 0))) () ) (dncp164i cmovc64a "64-bit cmovc" () "cmovc64a $cpccrn64,$cpccrm64,$cpcode24" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 5) cpccrn64 cpccrm64 cpcode24) (sequence ((SI dummy)) (set dummy cpcode24) (set cpccrn64 cpccrm64)) () ) (dncp164i cmovc64b "64-bit cmovc" () "cmovc64b $cpccrm64,$cpccrn64,$cpcode24" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 6) cpccrn64 cpccrm64 cpcode24) (sequence ((SI dummy)) (set dummy cpcode24) (set cpccrm64 cpccrn64)) () ) @ 1.1.1.1.4.1 log @file mep-rhcop.cpu was added on branch yamt-pagecache on 2014-05-22 16:00:32 +0000 @ text @d1 342 @ 1.1.1.1.4.2 log @sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments") @ text @a0 342 ; Copyright 2011 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; ; ; This file is part of the GNU Binutils. ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ; MA 02110-1301, USA. ;; This coprocessor definition is being used to verify vliw mode behaviour. ;; This is a mock-up done by Red Hat and is in no way supposed to represent ;; a real coprocessor. The hardware is defined in mep-core.cpu. ; Coprocessor registers (define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) (define-hardware (name h-cr64-rh-1) (comment "64-bit coprocessor registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register DI (32)) (set (index newval) (c-call VOID "h_cr64_set" index newval)) (get (index) (c-call DI "h_cr64_get" index)) (indices keyword "$c" (.map -reg-pair (.iota 32))) ) (define-hardware (name h-cr-rh-1) (comment "32-bit coprocessor registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register SI (32)) (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval))) (get (index) (trunc SI (c-call DI "h_cr64_get" index))) (indices keyword "$c" (.map -reg-pair (.iota 32))) ) (define-hardware (name h-ccr-rh-1) (comment "Coprocessor control registers for rh coprocessor for core 1") (attrs VIRTUAL rh-isa-1) (type register SI (64)) (set (index newval) (c-call VOID "h_ccr_set" index newval)) (get (index) (c-call DI "h_ccr_get" index)) (indices keyword "" (.map -ccr-reg-pair (.iota 64))) ) ; ifields For 16-bit insns (dnf f-cphigh4 "High 4 bits" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 0 4) (dnf f-cpcrn "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 4 5) (dnf f-cpcrm "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 11 5) (dnf f-uu2 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 2) (dnf f-uu3 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 3) (dnf f-cprm "Core GPR" ((ISA ext_cop1_16)) 12 4) ; ifields For 32-bit insns (some of the above are used too) ; Notes: ; ; f-alone: A value of 0111 means that the insn can run alone in ; one of the vliw modes. ; ; f-seg32: Together f-seg32 and f-seg32-a allow 64 different 32-bit ; f-seg32-a: insns to be defined. (dnf f-seg32 "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 9 3) (dnf f-alone "Run-alone indicator" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64)) 12 4) (dnf f-seg32-a "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 21 3) (dnf f-code8 "8 bit unsigned immediate" ((ISA ext_cop1_32)) 24 8) (dnf f-cpcrm-32 "Corpocessor Reg" ((ISA ext_cop1_32)) 16 5) ; ifields for 48-bit insns ; Note: Part of f-uu12 can be broken off later to enumerate ; any 48-bit insns that may be added. (dnf f-uu12 "Unusued 12 bits" ((ISA ext_cop1_48)) 4 12) (dnf f-code16a "Unsigned immediate" ((ISA ext_cop1_48)) 16 16) (dnf f-code16b "Unsigned immediate" ((ISA ext_cop1_48,ext_cop1_64)) 32 16) ; ifields for 64-bit insns (dnf f-uu8 "Unsused 8 bits" ((ISA ext_cop1_64)) 4 8) (dnf f-uu8a "Unused 13 bits" ((ISA ext_cop1_64)) 16 8) (dnf f-seg64 "Enumerate 64-bit insns" ((ISA ext_cop1_64)) 24 8) (dnf f-code16c "Unsigned immediate" ((ISA ext_cop1_64)) 48 16) (dnf f-cpcrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 5) (dnf f-cpcrm-64 "Coprocessor Register" ((ISA ext_cop1_64)) 37 4) (dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 41 23) (dnf f-cpccrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 4) (dnf f-cpccrm-64 "Core GPR" ((ISA ext_cop1_64)) 36 4) (dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 40 24) ; Operands for 16-bit insns (dnop cpcrn "cpcrn" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn) (dnop cpcrm "cpcrm" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm) (dnop cprm "cprm" ((ISA ext_cop1_16)) h-gpr f-cprm) ; Additional operands for 32-bit insns (dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8) ; Operands for 48-bit insns (dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a) (dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b) ; Additional operands for 64-bit insns (dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c) (dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64) (dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64) (dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64) (dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64) (dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23) (dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24) ; 16- and 32-bit nops can be defined as normal instructions without ; any problems. nops take no operands, so nops longer than 32 ; bits cannot be defined as normal insns since that would result in ; decodable bits beyond cgen's 32-bit boundary. As a result, we ; have to use macros and other real insns to create 48- and 64-bit nops. ; ; In addition, since the names of the nops that will be created as part ; of future insn sets are not known at this time, the assembler needs a ; fixed set of nop names that it can use for automatic nop insertion. ; The idea is that no matter what those insns are called, we don't want ; to have to change the C code in the assemblers vliw grouping validation ; and nop insertion routines. We therefore have to create macros for ; all nops to map the macro names which are known to the assembler to the ; names of the real nop insns. ; ; These emitted insns in these macros will need to be modified when ; new nops are defined in new coprocessor insn sets. ; A real 16-bit nop insn exists (dnmi cpnop16 "cpnop16" ((ISA ext_cop1_16)) "cpnop16" (emit cp16nop) ) ; A real 32-bit nop insn exists (dnmi cpnop32 "cpnop32" ((ISA ext_cop1_32)) "cpnop32" (emit cp32nop) ) ; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop. (dnmi cpnop48 "cpnop48" ((ISA ext_cop1_48)) "cpnop48" (emit cpf1nop (code16a 0) (code16b 0)) ) ; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop. (dnmi cpnop64 "cpnop64" ((ISA ext_cop1_64)) "cpnop64" (emit cpf3nop (code16b 0) (code16c 0)) ) (define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16)) (define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32)) (define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48)) (define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64)) ; 16-Bit Insns (dncp116i movcp16 "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16 $cpcrn,$cpcrm" (+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm) (set cpcrn cpcrm) () ) (dncp116i movcp16a "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16a $cpcrn,$cprm" (+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm) (set cpcrn (zext DI cprm)) () ) (dncp116i movcp16b "16-bit coprocessor move insn" (VLIW64_NO_MATCHING_NOP) "movcp16b $cprm,$cpcrn" (+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm) (set cprm (subword SI cpcrn 1)) () ) (dncp116i cp16nop "16-bit coprocessor nop" (VLIW64_NO_MATCHING_NOP) "cp16nop" (+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0)) (unimp "cp16nop") () ) ; 32-Bit Insns (dncp132i cp32nop "32-bit coprocessor nop" (VLIW64_NO_MATCHING_NOP) "cp32nop" (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) (f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0)) (unimp "cpnop32") () ) (dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests " (VLIW64_NO_MATCHING_NOP) "cpf2 $code8" (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7) (f-cpcrm-32 0) (f-seg32-a 1) code8) (unimp "cpf2") () ) ; 48-Bit Insns (dncp148i cpf1 "48-bit coprocessor helper insn" () "cpf1 $code16a,$code16b" (+ (f-cphigh4 4) (f-uu12 0) code16a code16b) (sequence ((HI result)) (if (eq code16a 0) (set pc (c-call USI "cop_exception" pc)) ; Set branch condition flags to value of code16a[0:3] ; Branch condition flags do not exist yet. (nop) ) ) () ) (dncp148i cpf1nop "48-bit coprocessor nop insn" () "cpf1nop $code16a,$code16b" (+ (f-cphigh4 5) (f-uu12 0) code16a code16b) (sequence ((HI result)) (set result (add code16a code16b)) ) () ) ; 64-Bit Insns (dncp164i cpf3 "64-bit coprocessor helper insn" () "cpf3 $code16b,$code16c" (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 0) code16b code16c) (sequence ((HI result)) (set result (add code16b code16c)) ) () ) (dncp164i cpf3nop "64-bit coprocessor helper insn" () "cpf3nop $code16b,$code16c" (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 7) code16b code16c) (sequence ((HI result)) (set result (add code16b code16c)) ) () ) (dncp164i cmov64a "64-bit cmov" () "cmov64a $cpcrn64,$cpcrm64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 1) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrn64 (zext DI cpcrm64))) () ) (dncp164i cmov64b "64-bit cmov" () "cmov64b $cpcrm64,$cpcrn64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 2) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrm64 (subword SI cpcrn64 1))) () ) (dncp164i cmovh64a "64-bit cmovh" () "cmovh64a $cpcrn64,$cpcrm64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 3) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1))))) () ) (dncp164i cmovh64b "64-bit cmovh" () "cmovh64b $cpcrm64,$cpcrn64,$cpcode23" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 4) cpcrn64 cpcrm64 cpcode23) (sequence ((SI dummy)) (set dummy cpcode23) (set cpcrm64 (subword SI cpcrn64 0))) () ) (dncp164i cmovc64a "64-bit cmovc" () "cmovc64a $cpccrn64,$cpccrm64,$cpcode24" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 5) cpccrn64 cpccrm64 cpcode24) (sequence ((SI dummy)) (set dummy cpcode24) (set cpccrn64 cpccrm64)) () ) (dncp164i cmovc64b "64-bit cmovc" () "cmovc64b $cpccrm64,$cpccrn64,$cpcode24" (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0) (f-seg64 6) cpccrn64 cpccrm64 cpcode24) (sequence ((SI dummy)) (set dummy cpcode24) (set cpccrm64 cpccrn64)) () ) @