head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC5:1.1.1.3 netbsd-11-0-RC4:1.1.1.3 netbsd-11-0-RC3:1.1.1.3 netbsd-11-0-RC2:1.1.1.3 netbsd-11-0-RC1:1.1.1.3 perseant-exfatfs-base-20250801:1.1.1.3 netbsd-11:1.1.1.3.0.18 netbsd-11-base:1.1.1.3 netbsd-10-1-RELEASE:1.1.1.3 perseant-exfatfs-base-20240630:1.1.1.3 perseant-exfatfs:1.1.1.3.0.16 perseant-exfatfs-base:1.1.1.3 netbsd-8-3-RELEASE:1.1.1.2 netbsd-9-4-RELEASE:1.1.1.3 netbsd-10-0-RELEASE:1.1.1.3 netbsd-10-0-RC6:1.1.1.3 netbsd-10-0-RC5:1.1.1.3 netbsd-10-0-RC4:1.1.1.3 netbsd-10-0-RC3:1.1.1.3 netbsd-10-0-RC2:1.1.1.3 netbsd-10-0-RC1:1.1.1.3 netbsd-10:1.1.1.3.0.14 netbsd-10-base:1.1.1.3 netbsd-9-3-RELEASE:1.1.1.3 gmp-6-2-1:1.1.1.3 cjep_sun2x-base1:1.1.1.3 cjep_sun2x:1.1.1.3.0.12 cjep_sun2x-base:1.1.1.3 cjep_staticlib_x-base1:1.1.1.3 netbsd-9-2-RELEASE:1.1.1.3 cjep_staticlib_x:1.1.1.3.0.10 cjep_staticlib_x-base:1.1.1.3 netbsd-9-1-RELEASE:1.1.1.3 gmp-6-2-0:1.1.1.3 phil-wifi-20200421:1.1.1.3 phil-wifi-20200411:1.1.1.3 is-mlppp:1.1.1.3.0.8 is-mlppp-base:1.1.1.3 phil-wifi-20200406:1.1.1.3 netbsd-8-2-RELEASE:1.1.1.2 netbsd-9-0-RELEASE:1.1.1.3 netbsd-9-0-RC2:1.1.1.3 netbsd-9-0-RC1:1.1.1.3 phil-wifi-20191119:1.1.1.3 netbsd-9:1.1.1.3.0.6 netbsd-9-base:1.1.1.3 phil-wifi-20190609:1.1.1.3 netbsd-8-1-RELEASE:1.1.1.2 netbsd-8-1-RC1:1.1.1.2 pgoyette-compat-merge-20190127:1.1.1.3 pgoyette-compat-20190127:1.1.1.3 pgoyette-compat-20190118:1.1.1.3 pgoyette-compat-1226:1.1.1.3 pgoyette-compat-1126:1.1.1.3 pgoyette-compat-1020:1.1.1.3 pgoyette-compat-0930:1.1.1.3 pgoyette-compat-0906:1.1.1.3 netbsd-7-2-RELEASE:1.1.1.2 pgoyette-compat-0728:1.1.1.3 netbsd-8-0-RELEASE:1.1.1.2 phil-wifi:1.1.1.3.0.4 phil-wifi-base:1.1.1.3 pgoyette-compat-0625:1.1.1.3 netbsd-8-0-RC2:1.1.1.2 pgoyette-compat-0521:1.1.1.3 pgoyette-compat-0502:1.1.1.3 pgoyette-compat-0422:1.1.1.3 netbsd-8-0-RC1:1.1.1.2 pgoyette-compat-0415:1.1.1.3 pgoyette-compat-0407:1.1.1.3 pgoyette-compat-0330:1.1.1.3 pgoyette-compat-0322:1.1.1.3 pgoyette-compat-0315:1.1.1.3 netbsd-7-1-2-RELEASE:1.1.1.2 pgoyette-compat:1.1.1.3.0.2 pgoyette-compat-base:1.1.1.3 netbsd-7-1-1-RELEASE:1.1.1.2 matt-nb8-mediatek:1.1.1.2.0.22 matt-nb8-mediatek-base:1.1.1.2 gmp-6-1-2:1.1.1.3 perseant-stdc-iso10646:1.1.1.2.0.20 perseant-stdc-iso10646-base:1.1.1.2 netbsd-8:1.1.1.2.0.18 netbsd-8-base:1.1.1.2 prg-localcount2-base3:1.1.1.2 prg-localcount2-base2:1.1.1.2 prg-localcount2-base1:1.1.1.2 prg-localcount2:1.1.1.2.0.16 prg-localcount2-base:1.1.1.2 pgoyette-localcount-20170426:1.1.1.2 bouyer-socketcan-base1:1.1.1.2 pgoyette-localcount-20170320:1.1.1.2 netbsd-7-1:1.1.1.2.0.14 netbsd-7-1-RELEASE:1.1.1.2 netbsd-7-1-RC2:1.1.1.2 netbsd-7-nhusb-base-20170116:1.1.1.2 bouyer-socketcan:1.1.1.2.0.12 bouyer-socketcan-base:1.1.1.2 pgoyette-localcount-20170107:1.1.1.2 netbsd-7-1-RC1:1.1.1.2 pgoyette-localcount-20161104:1.1.1.2 netbsd-7-0-2-RELEASE:1.1.1.2 localcount-20160914:1.1.1.2 netbsd-7-nhusb:1.1.1.2.0.10 netbsd-7-nhusb-base:1.1.1.2 pgoyette-localcount-20160806:1.1.1.2 pgoyette-localcount-20160726:1.1.1.2 pgoyette-localcount:1.1.1.2.0.8 pgoyette-localcount-base:1.1.1.2 netbsd-7-0-1-RELEASE:1.1.1.2 netbsd-7-0:1.1.1.2.0.6 netbsd-7-0-RELEASE:1.1.1.2 netbsd-7-0-RC3:1.1.1.2 netbsd-7-0-RC2:1.1.1.2 netbsd-7-0-RC1:1.1.1.2 netbsd-6-0-6-RELEASE:1.1.1.1 netbsd-6-1-5-RELEASE:1.1.1.1 netbsd-7:1.1.1.2.0.4 netbsd-7-base:1.1.1.2 yamt-pagecache-base9:1.1.1.2 yamt-pagecache-tag8:1.1.1.1 netbsd-6-1-4-RELEASE:1.1.1.1 netbsd-6-0-5-RELEASE:1.1.1.1 tls-earlyentropy:1.1.1.2.0.2 tls-earlyentropy-base:1.1.1.2 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1.1.2 riastradh-drm2-base3:1.1.1.2 netbsd-6-1-3-RELEASE:1.1.1.1 netbsd-6-0-4-RELEASE:1.1.1.1 gmp-5-1-3:1.1.1.2 netbsd-6-1-2-RELEASE:1.1.1.1 netbsd-6-0-3-RELEASE:1.1.1.1 netbsd-6-1-1-RELEASE:1.1.1.1 riastradh-drm2-base2:1.1.1.1 riastradh-drm2-base1:1.1.1.1 riastradh-drm2:1.1.1.1.0.12 riastradh-drm2-base:1.1.1.1 netbsd-6-1:1.1.1.1.0.16 netbsd-6-0-2-RELEASE:1.1.1.1 netbsd-6-1-RELEASE:1.1.1.1 netbsd-6-1-RC4:1.1.1.1 netbsd-6-1-RC3:1.1.1.1 agc-symver:1.1.1.1.0.14 agc-symver-base:1.1.1.1 netbsd-6-1-RC2:1.1.1.1 netbsd-6-1-RC1:1.1.1.1 yamt-pagecache-base8:1.1.1.1 netbsd-6-0-1-RELEASE:1.1.1.1 yamt-pagecache-base7:1.1.1.1 matt-nb6-plus-nbase:1.1.1.1 yamt-pagecache-base6:1.1.1.1 netbsd-6-0:1.1.1.1.0.10 netbsd-6-0-RELEASE:1.1.1.1 netbsd-6-0-RC2:1.1.1.1 tls-maxphys:1.1.1.1.0.8 tls-maxphys-base:1.1.1.2 matt-nb6-plus:1.1.1.1.0.6 matt-nb6-plus-base:1.1.1.1 netbsd-6-0-RC1:1.1.1.1 yamt-pagecache-base5:1.1.1.1 yamt-pagecache-base4:1.1.1.1 netbsd-6:1.1.1.1.0.4 netbsd-6-base:1.1.1.1 yamt-pagecache-base3:1.1.1.1 yamt-pagecache-base2:1.1.1.1 yamt-pagecache:1.1.1.1.0.2 yamt-pagecache-base:1.1.1.1 gmp-5-0-2:1.1.1.1 gmp:1.1.1; locks; strict; comment @;; @; 1.1 date 2011.06.20.05.54.40; author mrg; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2011.06.20.05.54.40; author mrg; state Exp; branches 1.1.1.1.2.1 1.1.1.1.8.1; next 1.1.1.2; 1.1.1.2 date 2013.11.29.07.49.48; author mrg; state Exp; branches; next 1.1.1.3; commitid L2Av4PuGmdoL39fx; 1.1.1.3 date 2017.08.22.09.40.49; author mrg; state Exp; branches; next ; commitid W5kmAIk8hwVpSb4A; 1.1.1.1.2.1 date 2014.05.22.14.09.02; author yamt; state Exp; branches; next ; commitid nx2BSsHy0NPeAxBx; 1.1.1.1.8.1 date 2014.08.19.23.59.51; author tls; state Exp; branches; next ; commitid jTnpym9Qu0o4R1Nx; desc @@ 1.1 log @Initial revision @ text @dnl PowerPC-32 mpn_mod_34lsub1 -- mpn remainder mod 2^24-1. dnl Copyright 2002, 2003, 2005, 2006, 2007 Free Software Foundation, Inc. dnl This file is part of the GNU MP Library. dnl The GNU MP Library is free software; you can redistribute it and/or modify dnl it under the terms of the GNU Lesser General Public License as published dnl by the Free Software Foundation; either version 3 of the License, or (at dnl your option) any later version. dnl The GNU MP Library is distributed in the hope that it will be useful, but dnl WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public dnl License for more details. dnl You should have received a copy of the GNU Lesser General Public License dnl along with the GNU MP Library. If not, see http://www.gnu.org/licenses/. include(`../config.m4') C cycles/limb C 603e: - C 604e: - C 75x (G3): - C 7400,7410 (G4): 1 simple load-use scheduling results in 0.75 C 744x,745x (G4+): 0.75 C ppc970: 0.75 C power4: - C power5: - C TODO C * Either start using the low-end masking constants, or remove them. C * Merge multiple feed-in cases into a parameterized code block. C * Reduce register usage. It should be possible to almost halve it. define(`up', `r3') define(`n', `r4') define(`a0', `v3') define(`a1', `v4') define(`a2', `v5') define(`c0', `v6') define(`c1', `v7') define(`c2', `v8') define(`z', `v9') define(`x0', `v10') define(`x1', `v11') define(`x2', `v12') define(`x3', `v13') define(`pv', `v14') define(`y0', `v0') define(`y1', `v1') define(`y2', `v2') define(`y3', `v15') ASM_START() PROLOGUE(mpn_mod_34lsub1) cmpwi cr0, n, 20 C tuned cutoff point bge L(large) li r9, 0 C result accumulator mulli r10, n, 0xb C 0xb = ceil(32/3) srwi. r10, r10, 5 C r10 = floor(n/3), n < 32 beq L(small_tail) mtctr r10 lwz r6, 0(up) lwz r7, 4(up) lwzu r8, 8(up) subf n, r10, n subf n, r10, n subf n, r10, n bdz L(small_end) ALIGN(16) L(los): rlwinm r0, r6, 0,8,31 add r9, r9, r0 C add 24b from u0 srwi r0, r6, 24 lwz r6, 4(up) rlwimi r0, r7, 8, 0x00ffff00 C --111100 add r9, r9, r0 C add 8b from u0 and 16b from u1 srwi r0, r7, 16 lwz r7, 8(up) rlwimi r0, r8, 16, 0x00ff0000 C --221111 add r9, r9, r0 C add 16b from u1 and 8b from u2 srwi r0, r8, 8 C --222222 lwzu r8, 12(up) add r9, r9, r0 C add 24b from u2 bdnz L(los) L(small_end): rlwinm r0, r6, 0,8,31 add r9, r9, r0 C add 24b from u0 srwi r0, r6, 24 rlwimi r0, r7, 8, 0x00ffff00 C --111100 add r9, r9, r0 C add 8b from u0 and 16b from u1 srwi r0, r7, 16 rlwimi r0, r8, 16, 0x00ff0000 C --221111 add r9, r9, r0 C add 16b from u1 and 8b from u2 srwi r0, r8, 8 C --222222 add r9, r9, r0 C add 24b from u2 addi up, up, 4 rlwinm r0, r9, 0,8,31 srwi r9, r9, 24 add r9, r9, r0 L(small_tail): cmpi cr0, n, 1 blt L(ret) lwz r6, 0(up) rlwinm r0, r6, 0,8,31 srwi r6, r6, 24 add r9, r9, r0 add r9, r9, r6 beq L(ret) lwz r6, 4(up) rlwinm r0, r6, 8,8,23 srwi r6, r6, 16 add r9, r9, r0 add r9, r9, r6 L(ret): mr r3, r9 blr L(large): mfspr r10, 256 oris r0, r10, 0xffff C Set VRSAVE bit 0-15 mtspr 256, r0 andi. r7, up, 15 vxor a0, v0, v0 lis r0, 0xaaaa vxor a1, v0, v0 ori r0, r0, 0xaaab vxor a2, v0, v0 li r5, 16 vxor c0, v0, v0 li r6, 32 vxor c1, v0, v0 LEAL( r11, cnsts) vxor c2, v0, v0 vxor z, v0, v0 beq L(aligned16) cmpwi cr7, r7, 8 bge cr7, L(na4) lvx a2, 0, up addi up, up, 16 vsldoi a2, a2, z, 4 vsldoi a2, z, a2, 12 addi n, n, 9 mulhwu r0, n, r0 srwi r0, r0, 3 C r0 = floor(n/12) mtctr r0 mulli r8, r0, 12 subf n, r8, n b L(2) L(na4): bne cr7, L(na8) lvx a1, 0, up addi up, up, -16 vsldoi a1, a1, z, 8 vsldoi a1, z, a1, 8 addi n, n, 6 mulhwu r0, n, r0 srwi r0, r0, 3 C r0 = floor(n/12) mtctr r0 mulli r8, r0, 12 subf n, r8, n b L(1) L(na8): lvx a0, 0, up vsldoi a0, a0, z, 12 vsldoi a0, z, a0, 4 addi n, n, 3 mulhwu r0, n, r0 srwi r0, r0, 3 C r0 = floor(n/12) mtctr r0 mulli r8, r0, 12 subf n, r8, n b L(0) L(aligned16): mulhwu r0, n, r0 srwi r0, r0, 3 C r0 = floor(n/12) mtctr r0 mulli r8, r0, 12 subf n, r8, n lvx a0, 0, up L(0): lvx a1, r5, up L(1): lvx a2, r6, up addi up, up, 48 L(2): bdz L(end) li r12, 256 li r9, 288 ALIGN(32) L(top): lvx v0, 0, up vaddcuw v10, a0, v0 vadduwm a0, a0, v0 vadduwm c0, c0, v10 lvx v1, r5, up vaddcuw v10, a1, v1 vadduwm a1, a1, v1 vadduwm c1, c1, v10 lvx v2, r6, up dcbt up, r12 dcbt up, r9 addi up, up, 48 vaddcuw v10, a2, v2 vadduwm a2, a2, v2 vadduwm c2, c2, v10 bdnz L(top) L(end): C n = 0...11 cmpwi cr0, n, 0 beq L(sum) cmpwi cr0, n, 4 ble L(tail.1..4) cmpwi cr0, n, 8 ble L(tail.5..8) L(tail.9..11): lvx v0, 0, up vaddcuw v10, a0, v0 vadduwm a0, a0, v0 vadduwm c0, c0, v10 lvx v1, r5, up vaddcuw v10, a1, v1 vadduwm a1, a1, v1 vadduwm c1, c1, v10 lvx v2, r6, up addi r8, r11, 96 rlwinm r3, n ,4,26,27 lvx v11, r3, r8 vand v2, v2, v11 vaddcuw v10, a2, v2 vadduwm a2, a2, v2 vadduwm c2, c2, v10 b L(sum) L(tail.5..8): lvx v0, 0, up vaddcuw v10, a0, v0 vadduwm a0, a0, v0 vadduwm c0, c0, v10 lvx v1, r5, up addi r8, r11, 96 rlwinm r3, n ,4,26,27 lvx v11, r3, r8 vand v1, v1, v11 vaddcuw v10, a1, v1 vadduwm a1, a1, v1 vadduwm c1, c1, v10 b L(sum) L(tail.1..4): lvx v0, 0, up addi r8, r11, 96 rlwinm r3, n ,4,26,27 lvx v11, r3, r8 vand v0, v0, v11 vaddcuw v10, a0, v0 vadduwm a0, a0, v0 vadduwm c0, c0, v10 L(sum): lvx pv, 0, r11 vperm x0, a0, z, pv C extract 4 24-bit field from a0 vperm y0, c2, z, pv lvx pv, r5, r11 vperm x1, a1, z, pv C extract 4 24-bit field from a1 vperm y1, c0, z, pv C extract 4 24-bit field from a1 lvx pv, r6, r11 vperm x2, a2, z, pv C extract 4 24-bit field from a1 vperm y2, c1, z, pv C extract 4 24-bit field from a1 li r10, 48 lvx pv, r10, r11 vperm x3, a0, z, pv C extract remaining/partial a0 fields vperm y3, c2, z, pv C extract remaining/partial a0 fields li r10, 64 lvx pv, r10, r11 vperm x3, a1, x3, pv C insert remaining/partial a1 fields vperm y3, c0, y3, pv C insert remaining/partial a1 fields li r10, 80 lvx pv, r10, r11 vperm x3, a2, x3, pv C insert remaining/partial a2 fields vperm y3, c1, y3, pv C insert remaining/partial a2 fields C We now have 4 128-bit accumulators to sum vadduwm x0, x0, x1 vadduwm x2, x2, x3 vadduwm x0, x0, x2 vadduwm y0, y0, y1 vadduwm y2, y2, y3 vadduwm y0, y0, y2 vadduwm x0, x0, y0 C Reduce 32-bit fields vsumsws x0, x0, z li r7, -16 C FIXME: does all ppc32 ABIs... stvx x0, r7, r1 C FIXME: ...support storing below sp? lwz r3, -4(r1) mtspr 256, r10 blr EPILOGUE() C load | v0 | v1 | v2 | C acc | a0 | a1 | a2 | C carry | c0 | c1 | c2 | C | 0 1 2 3 | 4 5 6 7 | 8 9 10 11 | 128 C |---|---|---|---|---|---|---|---|---|---|---|---| 32 C | | | | | | | | | | | | | | | | | 24 C | | | | | | | | | 48 C $---------------$---------------$---------------$---------------$ C | . . . . . . . . . . . . . . . | C |_______________________________________________________________| C | | | | | | | C <-hi16-> <--- 24 --> <--- 24 --> <--- 24 --> <--- 24 --> <-lo16-> DEF_OBJECT(cnsts,16) C Permutation vectors in the order they are used above C # 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f .byte 0x10,0x01,0x02,0x03, 0x10,0x06,0x07,0x00, 0x10,0x0b,0x04,0x05, 0x10,0x08,0x09,0x0a C a0 .byte 0x10,0x07,0x00,0x01, 0x10,0x04,0x05,0x06, 0x10,0x09,0x0a,0x0b, 0x10,0x0e,0x0f,0x08 C a1 .byte 0x10,0x00,0x01,0x02, 0x10,0x05,0x06,0x07, 0x10,0x0a,0x0b,0x04, 0x10,0x0f,0x08,0x09 C a2 .byte 0x10,0x0d,0x0e,0x0f, 0x10,0x10,0x10,0x0c, 0x10,0x10,0x10,0x10, 0x10,0x10,0x10,0x10 C part a0 .byte 0x10,0x11,0x12,0x13, 0x10,0x02,0x03,0x17, 0x10,0x10,0x0c,0x0d, 0x10,0x10,0x10,0x10 C part a1 .byte 0x10,0x11,0x12,0x13, 0x10,0x15,0x16,0x17, 0x10,0x03,0x1a,0x1b, 0x10,0x0c,0x0d,0x0e C part a2 C Masks for high end of number .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff .byte 0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00 C Masks for low end of number C .byte 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff C .byte 0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff C .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff C .byte 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff END_OBJECT(cnsts) @ 1.1.1.1 log @initial import of GMP 5.0.2. GNU MP is a library for arbitrary precision arithmetic, operating on signed integers, rational numbers, and floating point numbers. It has a rich set of functions, and the functions have a regular interface. GMP is necessary for GCC >= 4.2. @ text @@ 1.1.1.1.8.1 log @Rebase to HEAD as of a few days ago. @ text @d3 1 a3 2 dnl Copyright 2002, 2003, 2005, 2006, 2007, 2012 Free Software Foundation, dnl Inc. d138 1 a138 1 lis r9, 0xaaaa d140 1 a140 1 ori r9, r9, 0xaaab d146 1 a146 1 LEAL( r11, cnsts) C CAUTION clobbers r0 for elf, darwin d161 1 a161 1 mulhwu r0, n, r9 d177 1 a177 1 mulhwu r0, n, r9 d191 1 a191 1 mulhwu r0, n, r9 d200 1 a200 1 mulhwu r0, n, r9 @ 1.1.1.1.2.1 log @sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments") @ text @d3 1 a3 2 dnl Copyright 2002, 2003, 2005, 2006, 2007, 2012 Free Software Foundation, dnl Inc. d138 1 a138 1 lis r9, 0xaaaa d140 1 a140 1 ori r9, r9, 0xaaab d146 1 a146 1 LEAL( r11, cnsts) C CAUTION clobbers r0 for elf, darwin d161 1 a161 1 mulhwu r0, n, r9 d177 1 a177 1 mulhwu r0, n, r9 d191 1 a191 1 mulhwu r0, n, r9 d200 1 a200 1 mulhwu r0, n, r9 @ 1.1.1.2 log @initial import GMP 5.1.3 sources. changes include: fixes for: - mpn_sbpi1_div_qr_sec and mpn_sbpi1_div_r_sec - mpz_powm_ui - AMD family 11h - mpz_powm_sec and mpn_powm_sec - ASSERT() fixes - gcd, gcdext, and invert function fixes - some PPC division operations @ text @d3 1 a3 2 dnl Copyright 2002, 2003, 2005, 2006, 2007, 2012 Free Software Foundation, dnl Inc. d138 1 a138 1 lis r9, 0xaaaa d140 1 a140 1 ori r9, r9, 0xaaab d146 1 a146 1 LEAL( r11, cnsts) C CAUTION clobbers r0 for elf, darwin d161 1 a161 1 mulhwu r0, n, r9 d177 1 a177 1 mulhwu r0, n, r9 d191 1 a191 1 mulhwu r0, n, r9 d200 1 a200 1 mulhwu r0, n, r9 @ 1.1.1.3 log @initial import of GMP 6.1.2. main changes from 5.1.3 below. notes: - support for thumb-less ARM chips was in our port of 5.1.3, but a similar method has been provided upstream now - someone should look at the AVX failure reports, and fix them Changes between GMP version 6.1.0 and 6.1.1 FEATURES * Work around faulty cpuid on some recent Intel chips (this allows GMP to run on Skylake Pentiums). * Support thumb-less ARM chips. Changes between GMP version 6.0.* and 6.1.0 BUGS FIXED * The public function mpn_com is now correctly declared in gmp.h. * Healed possible failures of mpn_sec_sqr for non-cryptographic sizes for some obsolete CPUs. * Various problems related to precision for mpf have been fixed. * Fixed ABI incompatible stack alignment in calls from assembly code. * Fixed PIC bug in popcount affecting Intel processors using the 32-bit ABI. SPEEDUPS * Speedup for Intel Broadwell and Skylake through assembly code making use of new ADX instructions. * Square root is now faster when the remainder is not needed. Also the speed to compute the k-th root improved, for small sizes. FEATURES * New C++ functions gcd and lcm for mpz_class. * New public mpn functions mpn_divexact_1, mpn_zero_p, and mpn_cnd_swap. * New public mpq_cmp_z function, to efficiently compare rationals with integers. * Support for more 32-bit arm processors. * Support for AVX-less modern x86 CPUs. (Such support might be missing either because the CPU vendor chose to disable AVX, or because the running kernel lacks AVX context switch support.) * Support for NetBSD under Xen; we switch off AVX unconditionally under NetBSD since a bug in NetBSD makes AVX fail under Xen. MISC * Tuned values for FFT multiplications are provided for larger number on many platforms. Changes between GMP version 5.1.* and 6.0.0 BUGS FIXED * The function mpz_invert now considers any number invertible in Z/1Z. * The mpn multiply code now handles operands of more than 2^31 limbs correctly. (Note however that the mpz code is limited to 2^32 bits on 32-bit hosts and 2^37 bits on 64-bit hosts.) SPEEDUPS * Plain division of large operands is faster and more monotonous in operand size. * Major speedup for ARM, in particular ARM Cortex-A15, thanks to improved assembly. * Speedup for Intel Sandy Bridge, Ivy Bridge, Haswell, thanks to rewritten and vastly expanded assembly support. Speedup also for the older Core 2 and Nehalem. * Faster mixed arithmetic between mpq_class and double. FEATURES * Support for new Intel and AMD CPUs. * New public functions mpn_sec_mul and mpn_sec_sqr, implementing side-channel silent multiplication and squaring. * New public functions mpn_sec_div_qr and mpn_sec_div_r, implementing side-channel silent division. * New public functions mpn_cnd_add_n and mpn_cnd_sub_n. Side-channel silent conditional addition and subtraction. * New public function mpn_sec_powm, implementing side-channel silent modexp. * New public function mpn_sec_invert, implementing side-channel silent modular inversion. * Better support for applications which use the mpz_t type, but nevertheless need to call some of the lower-level mpn functions. See the documentation for mpz_limbs_read and related functions. @ text @d3 2 a4 1 dnl Copyright 2002, 2003, 2005-2007, 2012 Free Software Foundation, Inc. d7 1 a7 1 dnl d9 4 a12 14 dnl it under the terms of either: dnl dnl * the GNU Lesser General Public License as published by the Free dnl Software Foundation; either version 3 of the License, or (at your dnl option) any later version. dnl dnl or dnl dnl * the GNU General Public License as published by the Free Software dnl Foundation; either version 2 of the License, or (at your option) any dnl later version. dnl dnl or both in parallel, as here. dnl d15 5 a19 6 dnl or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License dnl for more details. dnl dnl You should have received copies of the GNU General Public License and the dnl GNU Lesser General Public License along with the GNU MP Library. If not, dnl see https://www.gnu.org/licenses/. a132 1 stwu r1, -32(r1) d334 3 a336 3 li r7, 16 stvx x0, r7, r1 lwz r3, 28(r1) a338 1 addi r1, r1, 32 @