head 1.2; access; symbols netbsd-11-1-RELEASE:1.2 netbsd-10-2-RELEASE:1.2 netbsd-9-5-RELEASE:1.2 netbsd-11-0-RELEASE:1.2 netbsd-11-0-RC7:1.2 netbsd-11-0-RC6:1.2 netbsd-11-0-RC5:1.2 netbsd-11-0-RC4:1.2 netbsd-11-0-RC3:1.2 netbsd-11-0-RC2:1.2 netbsd-11-0-RC1:1.2 perseant-exfatfs-base-20250801:1.2 netbsd-11:1.2.0.56 netbsd-11-base:1.2 netbsd-10-1-RELEASE:1.2 perseant-exfatfs-base-20240630:1.2 perseant-exfatfs:1.2.0.54 perseant-exfatfs-base:1.2 netbsd-8-3-RELEASE:1.2 netbsd-9-4-RELEASE:1.2 netbsd-10-0-RELEASE:1.2 netbsd-10-0-RC6:1.2 netbsd-10-0-RC5:1.2 netbsd-10-0-RC4:1.2 netbsd-10-0-RC3:1.2 netbsd-10-0-RC2:1.2 thorpej-ifq:1.2.0.52 thorpej-ifq-base:1.2 thorpej-altq-separation:1.2.0.50 thorpej-altq-separation-base:1.2 netbsd-10-0-RC1:1.2 netbsd-10:1.2.0.48 netbsd-10-base:1.2 bouyer-sunxi-drm:1.2.0.46 bouyer-sunxi-drm-base:1.2 netbsd-9-3-RELEASE:1.2 thorpej-i2c-spi-conf2:1.2.0.44 thorpej-i2c-spi-conf2-base:1.2 thorpej-futex2:1.2.0.42 thorpej-futex2-base:1.2 thorpej-cfargs2:1.2.0.40 thorpej-cfargs2-base:1.2 cjep_sun2x-base1:1.2 cjep_sun2x:1.2.0.38 cjep_sun2x-base:1.2 cjep_staticlib_x-base1:1.2 netbsd-9-2-RELEASE:1.2 cjep_staticlib_x:1.2.0.36 cjep_staticlib_x-base:1.2 thorpej-i2c-spi-conf:1.2.0.34 thorpej-i2c-spi-conf-base:1.2 thorpej-cfargs:1.2.0.32 thorpej-cfargs-base:1.2 thorpej-futex:1.2.0.30 thorpej-futex-base:1.2 netbsd-9-1-RELEASE:1.2 bouyer-xenpvh-base2:1.2 phil-wifi-20200421:1.2 bouyer-xenpvh-base1:1.2 phil-wifi-20200411:1.2 bouyer-xenpvh:1.2.0.28 bouyer-xenpvh-base:1.2 is-mlppp:1.2.0.26 is-mlppp-base:1.2 phil-wifi-20200406:1.2 netbsd-8-2-RELEASE:1.2 ad-namecache-base3:1.2 netbsd-9-0-RELEASE:1.2 netbsd-9-0-RC2:1.2 ad-namecache-base2:1.2 ad-namecache-base1:1.2 ad-namecache:1.2.0.24 ad-namecache-base:1.2 netbsd-9-0-RC1:1.2 phil-wifi-20191119:1.2 netbsd-9:1.2.0.22 netbsd-9-base:1.2 phil-wifi-20190609:1.2 netbsd-8-1-RELEASE:1.2 netbsd-8-1-RC1:1.2 isaki-audio2:1.2.0.20 isaki-audio2-base:1.2 pgoyette-compat-merge-20190127:1.2 pgoyette-compat-20190127:1.2 pgoyette-compat-20190118:1.2 pgoyette-compat-1226:1.2 pgoyette-compat-1126:1.2 pgoyette-compat-1020:1.2 pgoyette-compat-0930:1.2 pgoyette-compat-0906:1.2 netbsd-7-2-RELEASE:1.1 pgoyette-compat-0728:1.2 netbsd-8-0-RELEASE:1.2 phil-wifi:1.2.0.18 phil-wifi-base:1.2 pgoyette-compat-0625:1.2 netbsd-8-0-RC2:1.2 pgoyette-compat-0521:1.2 pgoyette-compat-0502:1.2 pgoyette-compat-0422:1.2 netbsd-8-0-RC1:1.2 pgoyette-compat-0415:1.2 pgoyette-compat-0407:1.2 pgoyette-compat-0330:1.2 pgoyette-compat-0322:1.2 pgoyette-compat-0315:1.2 netbsd-7-1-2-RELEASE:1.1 pgoyette-compat:1.2.0.16 pgoyette-compat-base:1.2 netbsd-7-1-1-RELEASE:1.1 tls-maxphys-base-20171202:1.2 matt-nb8-mediatek:1.2.0.14 matt-nb8-mediatek-base:1.2 nick-nhusb-base-20170825:1.2 perseant-stdc-iso10646:1.2.0.12 perseant-stdc-iso10646-base:1.2 netbsd-8:1.2.0.10 netbsd-8-base:1.2 prg-localcount2-base3:1.2 prg-localcount2-base2:1.2 prg-localcount2-base1:1.2 prg-localcount2:1.2.0.8 prg-localcount2-base:1.2 pgoyette-localcount-20170426:1.2 bouyer-socketcan-base1:1.2 jdolecek-ncq:1.2.0.6 jdolecek-ncq-base:1.2 pgoyette-localcount-20170320:1.2 netbsd-7-1:1.1.0.22 netbsd-7-1-RELEASE:1.1 netbsd-7-1-RC2:1.1 nick-nhusb-base-20170204:1.2 netbsd-7-nhusb-base-20170116:1.1 bouyer-socketcan:1.2.0.4 bouyer-socketcan-base:1.2 pgoyette-localcount-20170107:1.2 netbsd-7-1-RC1:1.1 nick-nhusb-base-20161204:1.2 pgoyette-localcount-20161104:1.2 netbsd-7-0-2-RELEASE:1.1 nick-nhusb-base-20161004:1.2 localcount-20160914:1.2 netbsd-7-nhusb:1.1.0.20 netbsd-7-nhusb-base:1.1 pgoyette-localcount-20160806:1.2 pgoyette-localcount-20160726:1.2 pgoyette-localcount:1.2.0.2 pgoyette-localcount-base:1.2 nick-nhusb-base-20160907:1.2 nick-nhusb-base-20160529:1.2 netbsd-7-0-1-RELEASE:1.1 nick-nhusb-base-20160422:1.2 nick-nhusb-base-20160319:1.2 nick-nhusb-base-20151226:1.1 netbsd-7-0:1.1.0.18 netbsd-7-0-RELEASE:1.1 nick-nhusb-base-20150921:1.1 netbsd-7-0-RC3:1.1 netbsd-7-0-RC2:1.1 netbsd-7-0-RC1:1.1 nick-nhusb-base-20150606:1.1 nick-nhusb-base-20150406:1.1 nick-nhusb:1.1.0.16 nick-nhusb-base:1.1 netbsd-7:1.1.0.14 netbsd-7-base:1.1 yamt-pagecache:1.1.0.12 yamt-pagecache-base9:1.1 tls-earlyentropy:1.1.0.10 tls-earlyentropy-base:1.1 riastradh-xf86-video-intel-2-7-1-pre-2-21-15:1.1 riastradh-drm2-base3:1.1 rmind-smpnet-nbase:1.1 riastradh-drm2-base2:1.1 riastradh-drm2-base1:1.1 riastradh-drm2:1.1.0.8 riastradh-drm2-base:1.1 rmind-smpnet:1.1.0.6 rmind-smpnet-base:1.1 tls-maxphys-base:1.1 tls-maxphys:1.1.0.4 khorben-n900:1.1.0.2; locks; strict; comment @// @; 1.2 date 2016.02.01.17.44.19; author christos; state Exp; branches; next 1.1; commitid GbEW0hzxyGTwQeTy; 1.1 date 2013.04.28.12.11.27; author kiyohara; state Exp; branches 1.1.4.1 1.1.12.1 1.1.16.1; next ; 1.1.4.1 date 2013.04.28.12.11.27; author tls; state dead; branches; next 1.1.4.2; commitid eVjr9caYRQbRGHUw; 1.1.4.2 date 2013.06.23.06.20.03; author tls; state Exp; branches; next 1.1.4.3; commitid eVjr9caYRQbRGHUw; 1.1.4.3 date 2017.12.03.11.36.02; author jdolecek; state Exp; branches; next ; commitid XcIYRZTAh1LmerhA; 1.1.12.1 date 2013.04.28.12.11.27; author yamt; state dead; branches; next 1.1.12.2; commitid VUUXuyNWnt3AKwBx; 1.1.12.2 date 2014.05.22.11.39.39; author yamt; state Exp; branches; next ; commitid VUUXuyNWnt3AKwBx; 1.1.16.1 date 2016.03.19.11.29.58; author skrll; state Exp; branches; next ; commitid 2PHKtPSg1vDV9fZy; desc @@ 1.2 log @PR/50740: David Binderman: Provide a copy constructor. @ text @/* $NetBSD: epoc32.cpp,v 1.1 2013/04/28 12:11:27 kiyohara Exp $ */ /* * Copyright (c) 2013 KIYOHARA Takashi * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "cpu.h" #include "e32boot.h" #include "ekern.h" #include "epoc32.h" #include "arm/armreg.h" #include "arm/arm32/pte.h" static inline void AllowAllDomains(void) { TUint domains; #define ALL_DOMAINS(v) \ (((v) << 28) | \ ((v) << 24) | \ ((v) << 20) | \ ((v) << 16) | \ ((v) << 12) | \ ((v) << 8) | \ ((v) << 4) | \ ((v) << 0)) domains = ALL_DOMAINS(0xf); __asm("mcr p15, 0, %0, c3, c0" : : "r"(domains)); } EPOC32::EPOC32(const EPOC32& c) { cpu = c.cpu; } EPOC32::EPOC32(void) { TUint procid; __asm("mrc p15, 0, %0, c0, c0" : "=r"(procid)); if (procid == CPU_ID_SA1100) { cpu = new SA1100; } else if ((procid & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) { if (CPU_ID_IS7(procid)) { if ((procid & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3) cpu = new ARM7; else cpu = new ARM7TDMI; } } } EPOC32::~EPOC32(void) { } TAny * EPOC32::GetPhysicalAddress(TAny *address) { TUint l1Index, l1, pageOffset, pa, va; TUint *l1Tbl; AllowAllDomains(); l1Tbl = GetTTB(); va = (TUint)address; pa = pageOffset = 0; l1Index = (va & L1_ADDR_BITS) >> L1_S_SHIFT; l1 = *(l1Tbl + l1Index); switch (l1 & L1_TYPE_MASK) { case L1_TYPE_INV: case L1_TYPE_F: return NULL; case L1_TYPE_S: pa = l1 & L1_S_ADDR_MASK; pageOffset = va & L1_S_OFFSET; break; case L1_TYPE_C: { TUint *l2Tbl, tag; l2Tbl = (TUint *)(l1 & L1_C_ADDR_MASK); tag = MapPhysicalAddress(l2Tbl, (TAny **)&l2Tbl); pa = *(l2Tbl + ((va & L2_ADDR_BITS) >> 12)); UnmapPhysicalAddress(l2Tbl, tag); switch (pa & L2_TYPE_MASK) { case L2_TYPE_L: pa &= L2_L_FRAME; pageOffset = va & L2_L_OFFSET; break; case L2_TYPE_S: pa &= L2_S_FRAME; pageOffset = va & L2_S_OFFSET; break; default: pageOffset = 0xffffffff; /* XXXX */ } } } return (TAny *)(pa | pageOffset); } TUint EPOC32::MapPhysicalAddress(TAny *pa, TAny **vap) { TUint *l1Tbl, l1Index, l1, tag; AllowAllDomains(); l1Tbl = GetTTB(); l1Index = ((TUint)pa & L1_ADDR_BITS) >> L1_S_SHIFT; l1 = ((TUint)pa & L1_S_ADDR_MASK) | L1_S_AP(AP_KRW) | L1_S_IMP | L1_TYPE_S; tag = *(l1Tbl + l1Index); *(l1Tbl + l1Index) = l1; cpu->cacheFlush(); cpu->tlbFlush(); *vap = pa; return tag; } void EPOC32::UnmapPhysicalAddress(TAny *address, TUint tag) { TUint *l1Tbl, l1Index, pa; AllowAllDomains(); l1Tbl = GetTTB(); pa = (TUint)address; l1Index = (pa & L1_ADDR_BITS) >> L1_S_SHIFT; *(l1Tbl + l1Index) = tag; cpu->cacheFlush(); cpu->tlbFlush(); } @ 1.1 log @Add new port NetBSD/epoc32. @ text @d1 1 a1 1 /* $NetBSD$ */ d60 5 @ 1.1.16.1 log @Sync with HEAD @ text @d1 1 a1 1 /* $NetBSD: epoc32.cpp,v 1.2 2016/02/01 17:44:19 christos Exp $ */ a59 5 EPOC32::EPOC32(const EPOC32& c) { cpu = c.cpu; } @ 1.1.12.1 log @file epoc32.cpp was added on branch yamt-pagecache on 2014-05-22 11:39:39 +0000 @ text @d1 168 @ 1.1.12.2 log @sync with head. for a reference, the tree before this commit was tagged as yamt-pagecache-tag8. this commit was splitted into small chunks to avoid a limitation of cvs. ("Protocol error: too many arguments") @ text @a0 168 /* $NetBSD$ */ /* * Copyright (c) 2013 KIYOHARA Takashi * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "cpu.h" #include "e32boot.h" #include "ekern.h" #include "epoc32.h" #include "arm/armreg.h" #include "arm/arm32/pte.h" static inline void AllowAllDomains(void) { TUint domains; #define ALL_DOMAINS(v) \ (((v) << 28) | \ ((v) << 24) | \ ((v) << 20) | \ ((v) << 16) | \ ((v) << 12) | \ ((v) << 8) | \ ((v) << 4) | \ ((v) << 0)) domains = ALL_DOMAINS(0xf); __asm("mcr p15, 0, %0, c3, c0" : : "r"(domains)); } EPOC32::EPOC32(void) { TUint procid; __asm("mrc p15, 0, %0, c0, c0" : "=r"(procid)); if (procid == CPU_ID_SA1100) { cpu = new SA1100; } else if ((procid & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) { if (CPU_ID_IS7(procid)) { if ((procid & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3) cpu = new ARM7; else cpu = new ARM7TDMI; } } } EPOC32::~EPOC32(void) { } TAny * EPOC32::GetPhysicalAddress(TAny *address) { TUint l1Index, l1, pageOffset, pa, va; TUint *l1Tbl; AllowAllDomains(); l1Tbl = GetTTB(); va = (TUint)address; pa = pageOffset = 0; l1Index = (va & L1_ADDR_BITS) >> L1_S_SHIFT; l1 = *(l1Tbl + l1Index); switch (l1 & L1_TYPE_MASK) { case L1_TYPE_INV: case L1_TYPE_F: return NULL; case L1_TYPE_S: pa = l1 & L1_S_ADDR_MASK; pageOffset = va & L1_S_OFFSET; break; case L1_TYPE_C: { TUint *l2Tbl, tag; l2Tbl = (TUint *)(l1 & L1_C_ADDR_MASK); tag = MapPhysicalAddress(l2Tbl, (TAny **)&l2Tbl); pa = *(l2Tbl + ((va & L2_ADDR_BITS) >> 12)); UnmapPhysicalAddress(l2Tbl, tag); switch (pa & L2_TYPE_MASK) { case L2_TYPE_L: pa &= L2_L_FRAME; pageOffset = va & L2_L_OFFSET; break; case L2_TYPE_S: pa &= L2_S_FRAME; pageOffset = va & L2_S_OFFSET; break; default: pageOffset = 0xffffffff; /* XXXX */ } } } return (TAny *)(pa | pageOffset); } TUint EPOC32::MapPhysicalAddress(TAny *pa, TAny **vap) { TUint *l1Tbl, l1Index, l1, tag; AllowAllDomains(); l1Tbl = GetTTB(); l1Index = ((TUint)pa & L1_ADDR_BITS) >> L1_S_SHIFT; l1 = ((TUint)pa & L1_S_ADDR_MASK) | L1_S_AP(AP_KRW) | L1_S_IMP | L1_TYPE_S; tag = *(l1Tbl + l1Index); *(l1Tbl + l1Index) = l1; cpu->cacheFlush(); cpu->tlbFlush(); *vap = pa; return tag; } void EPOC32::UnmapPhysicalAddress(TAny *address, TUint tag) { TUint *l1Tbl, l1Index, pa; AllowAllDomains(); l1Tbl = GetTTB(); pa = (TUint)address; l1Index = (pa & L1_ADDR_BITS) >> L1_S_SHIFT; *(l1Tbl + l1Index) = tag; cpu->cacheFlush(); cpu->tlbFlush(); } @ 1.1.4.1 log @file epoc32.cpp was added on branch tls-maxphys on 2013-06-23 06:20:03 +0000 @ text @d1 168 @ 1.1.4.2 log @resync from head @ text @a0 168 /* $NetBSD$ */ /* * Copyright (c) 2013 KIYOHARA Takashi * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include #include #include #include "cpu.h" #include "e32boot.h" #include "ekern.h" #include "epoc32.h" #include "arm/armreg.h" #include "arm/arm32/pte.h" static inline void AllowAllDomains(void) { TUint domains; #define ALL_DOMAINS(v) \ (((v) << 28) | \ ((v) << 24) | \ ((v) << 20) | \ ((v) << 16) | \ ((v) << 12) | \ ((v) << 8) | \ ((v) << 4) | \ ((v) << 0)) domains = ALL_DOMAINS(0xf); __asm("mcr p15, 0, %0, c3, c0" : : "r"(domains)); } EPOC32::EPOC32(void) { TUint procid; __asm("mrc p15, 0, %0, c0, c0" : "=r"(procid)); if (procid == CPU_ID_SA1100) { cpu = new SA1100; } else if ((procid & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) { if (CPU_ID_IS7(procid)) { if ((procid & CPU_ID_7ARCH_MASK) == CPU_ID_7ARCH_V3) cpu = new ARM7; else cpu = new ARM7TDMI; } } } EPOC32::~EPOC32(void) { } TAny * EPOC32::GetPhysicalAddress(TAny *address) { TUint l1Index, l1, pageOffset, pa, va; TUint *l1Tbl; AllowAllDomains(); l1Tbl = GetTTB(); va = (TUint)address; pa = pageOffset = 0; l1Index = (va & L1_ADDR_BITS) >> L1_S_SHIFT; l1 = *(l1Tbl + l1Index); switch (l1 & L1_TYPE_MASK) { case L1_TYPE_INV: case L1_TYPE_F: return NULL; case L1_TYPE_S: pa = l1 & L1_S_ADDR_MASK; pageOffset = va & L1_S_OFFSET; break; case L1_TYPE_C: { TUint *l2Tbl, tag; l2Tbl = (TUint *)(l1 & L1_C_ADDR_MASK); tag = MapPhysicalAddress(l2Tbl, (TAny **)&l2Tbl); pa = *(l2Tbl + ((va & L2_ADDR_BITS) >> 12)); UnmapPhysicalAddress(l2Tbl, tag); switch (pa & L2_TYPE_MASK) { case L2_TYPE_L: pa &= L2_L_FRAME; pageOffset = va & L2_L_OFFSET; break; case L2_TYPE_S: pa &= L2_S_FRAME; pageOffset = va & L2_S_OFFSET; break; default: pageOffset = 0xffffffff; /* XXXX */ } } } return (TAny *)(pa | pageOffset); } TUint EPOC32::MapPhysicalAddress(TAny *pa, TAny **vap) { TUint *l1Tbl, l1Index, l1, tag; AllowAllDomains(); l1Tbl = GetTTB(); l1Index = ((TUint)pa & L1_ADDR_BITS) >> L1_S_SHIFT; l1 = ((TUint)pa & L1_S_ADDR_MASK) | L1_S_AP(AP_KRW) | L1_S_IMP | L1_TYPE_S; tag = *(l1Tbl + l1Index); *(l1Tbl + l1Index) = l1; cpu->cacheFlush(); cpu->tlbFlush(); *vap = pa; return tag; } void EPOC32::UnmapPhysicalAddress(TAny *address, TUint tag) { TUint *l1Tbl, l1Index, pa; AllowAllDomains(); l1Tbl = GetTTB(); pa = (TUint)address; l1Index = (pa & L1_ADDR_BITS) >> L1_S_SHIFT; *(l1Tbl + l1Index) = tag; cpu->cacheFlush(); cpu->tlbFlush(); } @ 1.1.4.3 log @update from HEAD @ text @a59 5 EPOC32::EPOC32(const EPOC32& c) { cpu = c.cpu; } @