head 1.1; access; symbols; locks; strict; comment @ * @; 1.1 date 2026.09.28.20.41.01; author rkujawa; state Exp; branches; next ; commitid qChHdbcPYQzpBqXG; desc @@ 1.1 log @Fixes and features for PPC440 core, PPC460EX chip, Sam460ex board. - Add ebc - PPC440 family External Bus Controller driver. - Add samfpga - Driver for Sam460ex on-board FPGA (provides 80 GPIOs, soft power off, 3x led(4), etc. Lives on the ebc. - Enable PPC460EX on-chip GPIO via gpio_opb. - Implement a bunch of workarounds for 440/460 hardware bugs. - Enable pm2fb in SAM460EX config (necessary fixes to pm2fb pending commit). - Disable OHCI in SAM460EX config - due to hardware bug operating two AHB masters at the same time may cause lockups. And it sure does, there's no known software workaround. - Don't allow passing PSL_FP from MSR userland bits (userland can cause panic). - Fix ghost interrupt deliveries where asserted line re-entered the exception. - Ensure interrupt level-mask flag is set by default. - Tag mmaped DMA address as cacheable unless memory was explicitly allocated as uncached (only for 440, OEA probably could use it too). - Fix up 440 TLB decoding in ddb. - Fix pmap handling of reserved windows that may be mapped from userland. - Refactor L2 cache handling, make it more maintainable and in style of other ports. - Decode PLL straps and let the user know at what base frequency does the board run (useful if the user wants to apply firmware update, because images are built for different base freqs). - Minor trap stuff: decode and clear MCSR in a single helper, dump TLB on parity checks, user-mode MCHK are now SIGBUS. - Try to sanely handle the fact that 460EX has SERDES PHY that can either serve PCIe port or SATA - detect that and attach drivers accordingly. @ text @/* $NetBSD$ */ /*- * Copyright (c) 2026 The NetBSD Foundation, Inc. * All rights reserved. * * This code is derived from software contributed to The NetBSD Foundation * by Radoslaw Kujawa. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * PPC 4xx External Bus Controller. * * Currently depends on the firmware programming EBC0_BnCR registers. */ #include __KERNEL_RCSID(0, "$NetBSD$"); #include "locators.h" #include #include #include #include #include #include #include #include #include #include #define EBC_NBANK_MAX 8 /* EBC0_BnCR */ #define EBC_BCR_BAS 0xfff00000 /* base address */ #define EBC_BCR_BS 0x000e0000 /* bank size, 1MB << n */ #define EBC_BCR_BS_SHIFT 17 #define EBC_BCR_BU 0x00018000 /* bank usage */ #define EBC_BCR_BU_SHIFT 15 #define EBC_BCR_BW 0x00006000 /* bus width, 8 << n */ #define EBC_BCR_BW_SHIFT 13 struct ebc_softc { device_t sc_dev; struct powerpc_bus_space sc_bst; char sc_ex_storage[EXTENT_FIXED_STORAGE_SIZE(8)] __aligned(8); int sc_nbank; }; static int ebc_match(device_t, cfdata_t, void *); static void ebc_attach(device_t, device_t, void *); static int ebc_print(void *, const char *); static uint32_t ebc_read_bcr(int); CFATTACH_DECL_NEW(ebc, sizeof(struct ebc_softc), ebc_match, ebc_attach, NULL, NULL); static int ebc_match(device_t parent, cfdata_t cf, void *aux) { struct plb_attach_args * const paa = aux; return strcmp(paa->plb_name, cf->cf_name) == 0; } static void ebc_attach(device_t parent, device_t self, void *aux) { struct ebc_softc * const sc = device_private(self); struct plb_attach_args * const paa = aux; struct ebc_attach_args eaa; int locs[EBCCF_NLOCS]; int bank; sc->sc_dev = self; switch (mfpvr() >> 16) { case AMCC460EX: sc->sc_nbank = 6; break; default: sc->sc_nbank = EBC_NBANK_MAX; break; } aprint_naive("\n"); aprint_normal(": External Bus Controller, %d banks\n", sc->sc_nbank); sc->sc_bst.pbs_flags = _BUS_SPACE_BIG_ENDIAN | _BUS_SPACE_MEM_TYPE; sc->sc_bst.pbs_base = 0; sc->sc_bst.pbs_limit = 0xffffffff; if (bus_space_init(&sc->sc_bst, "ebc", sc->sc_ex_storage, sizeof(sc->sc_ex_storage)) != 0) { aprint_error_dev(self, "can't init bus space\n"); return; } for (bank = 0; bank < sc->sc_nbank; bank++) { const uint32_t bcr = ebc_read_bcr(bank); eaa.ebc_usage = __SHIFTOUT(bcr, EBC_BCR_BU); if (eaa.ebc_usage == EBC_USAGE_DISABLED) continue; eaa.ebc_bt = &sc->sc_bst; eaa.ebc_dmat = paa->plb_dmat; eaa.ebc_bank = bank; eaa.ebc_addr = bcr & EBC_BCR_BAS; eaa.ebc_size = 0x00100000 << __SHIFTOUT(bcr, EBC_BCR_BS); eaa.ebc_width = 8 << __SHIFTOUT(bcr, EBC_BCR_BW); aprint_verbose_dev(self, "bank %d: 0x%08" PRIxBUSADDR "-0x%08" PRIxBUSADDR ", %d-bit, %s\n", bank, eaa.ebc_addr, eaa.ebc_addr + eaa.ebc_size - 1, eaa.ebc_width, eaa.ebc_usage == EBC_USAGE_RW ? "r/w" : eaa.ebc_usage == EBC_USAGE_RO ? "r/o" : "w/o"); /* Refuse banks we didn't pin. */ if (ppc4xx_tlb_mapiodev(eaa.ebc_addr, PAGE_SIZE) == NULL) { aprint_verbose_dev(self, "bank %d: no reserved mapping, skipped\n", bank); continue; } locs[EBCCF_BANK] = bank; config_found(self, &eaa, ebc_print, CFARGS(.submatch = config_stdsubmatch, .locators = locs)); } } static int ebc_print(void *aux, const char *pnp) { struct ebc_attach_args * const eaa = aux; if (pnp != NULL) aprint_normal("device at %s", pnp); aprint_normal(" bank %d addr 0x%08" PRIxBUSADDR, eaa->ebc_bank, eaa->ebc_addr); return UNCONF; } static uint32_t ebc_read_bcr(int bank) { mtdcr(DCR_EBC0_CFGADDR, DCR_EBC0_B0CR + bank); return mfdcr(DCR_EBC0_CFGDATA); } @