head	1.12;
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	netbsd-11-0-RC4:1.11
	netbsd-11-0-RC3:1.11
	netbsd-11-0-RC2:1.11
	netbsd-11-0-RC1:1.11
	perseant-exfatfs-base-20250801:1.11
	netbsd-11:1.11.0.2
	netbsd-11-base:1.11
	perseant-exfatfs-base-20240630:1.3
	perseant-exfatfs:1.3.0.2
	perseant-exfatfs-base:1.3;
locks; strict;
comment	@# @;


1.12
date	2025.09.06.15.44.04;	author thorpej;	state Exp;
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1.11
date	2025.02.08.16.12.20;	author skrll;	state Exp;
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1.10
date	2025.01.03.11.49.04;	author skrll;	state Exp;
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1.9
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1.8
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1.7
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1.6
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1.5
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1.4
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1.3
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1.3.2.1
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desc
@@


1.12
log
@Step towards modularizing the Flattened Device Tree code.

Define attributes for each of the specific device bindings: clock,
dai, dma, gpio, i2c, iommu, mbox, mmc_pwrseq, phy, power, power domain,
pwm, regulator, reset controller, spi, system controller, pin
controller.  Include these support files only if either a provider
or consumer with one of these attributes is present in the kernel
config.

Add the necessary attributes to the device / attach declarations for
each provider and consumer.

There are some bindings that are consumed by generic code (iommu, pinctrl,
power, power domain).  Provide weak stubs for these routines to handle
situations where there is no provider.

No actual code changed; NFCI.
@
text
@#	$NetBSD: files.starfive,v 1.11 2025/02/08 16:12:20 skrll Exp $
#
# Configuration info for StarFive SoCs
#

# JH71x0 Clock controllers
device	jh7100clkc: fdt_clock
attach	jh7100clkc at fdt with jh7100_clkc
file	arch/riscv/starfive/jh7100_clkc.c		jh7100_clkc

device	jh7110clkc: fdt_clock, fdt_reset
attach	jh7110clkc at fdt with jh7110_clkc
file	arch/riscv/starfive/jh7110_clkc.c		jh7110_clkc

file	arch/riscv/starfive/jh71x0_clkc.c		jh7100_clkc | jh7110_clkc

# JH71x0 USB
device	jh71x0usb: fdt_syscon
attach	jh71x0usb at fdt with jh71x0_usb
file	arch/riscv/starfive/jh71x0_usb.c		jh71x0_usb

# JH7100 Pin control
device	jh7100pinctrl: fdt_gpio, fdt_pinctrl
attach	jh7100pinctrl at fdt with jh7100_pinctrl
file	arch/riscv/starfive/jh7100_pinctrl.c		jh7100_pinctrl

# JH7100 Pin control
device	jh7110pinctrl: fdt_gpio, fdt_pinctrl
attach	jh7110pinctrl at fdt with jh7110_pinctrl
file	arch/riscv/starfive/jh7110_pinctrl.c		jh7110_pinctrl

# Ethernet
# JH7100 GMAC
attach	awge at fdt with jh7100_gmac: fdt_clock, fdt_reset, fdt_syscon

# JH7110 EOQS
attach	eqos at fdt with jh7110_eqos: fdt_clock, fdt_reset, fdt_syscon

file	arch/riscv/starfive/jh7100_gmac.c		jh7100_gmac
file	arch/riscv/starfive/jh7110_eqos.c		jh7110_eqos
file	arch/riscv/starfive/jh71x0_eth.c		jh7100_gmac | jh7110_eqos

# JH7110 PCIe PHY
device	jh7110pciephy: fdt_phy
attach	jh7110pciephy at fdt with jh7110_pciephy
file	arch/riscv/starfive/jh7110_pciephy.c		jh7110_pciephy

# JH7110 PCIe
device	jh7110pcie: fdt_clock, fdt_gpio, fdt_reset, fdt_syscon, pcibus, pcihost_fdt
attach	jh7110pcie at fdt with jh7110_pcie
file	arch/riscv/starfive/jh7110_pcie.c		jh7110_pcie

# JH7110 system control
device	jh7110syscon: fdt_syscon
attach	jh7110syscon at fdt with jh7110_syscon
file	arch/riscv/starfive/jh7110_syscon.c		jh7110_syscon

# JH71x0 temperature sensor
device	jh71x0temp: fdt_reset
attach	jh71x0temp at fdt with jh71x0_temp
file	arch/riscv/starfive/jh71x0_temp.c		jh71x0_temp

# JH7110 TRNG
device	jh7110trng: fdt_reset
attach	jh7110trng at fdt with jh7110_trng
file	arch/riscv/starfive/jh7110_trng.c		jh7110_trng
@


1.11
log
@risc-v: add a JH7110 TRNG driver
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.10 2025/01/03 11:49:04 skrll Exp $
d7 1
a7 1
device	jh7100clkc
d11 1
a11 1
device	jh7110clkc
d18 1
a18 1
device	jh71x0usb
d23 1
a23 1
device	jh7100pinctrl
d28 1
a28 1
device	jh7110pinctrl
d34 1
a34 1
attach	awge at fdt with jh7100_gmac
d37 1
a37 1
attach	eqos at fdt with jh7110_eqos
d44 1
a44 1
device	jh7110pciephy
d49 1
a49 1
device	jh7110pcie: pcibus, pcihost_fdt
d54 1
a54 1
device	jh7110syscon
d59 1
a59 1
device	jh71x0temp
d64 1
a64 1
device	jh7110trng
@


1.10
log
@risc-v: add a StarFive JH71[01]0 temperature sensor driver
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.9 2025/01/01 17:53:08 skrll Exp $
d62 5
@


1.9
log
@risc-v: add support for PCI and the PCIe controller in the JH7110 SoC.

Testing as working with xhci and nvme on VisionFive2.

Uses legacy PCI interrupts currently. MSIs to be added later.

pcihost_fdt code is 99% the same as the Arm version and should be shared.
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.8 2024/11/11 20:30:08 skrll Exp $
d57 5
@


1.8
log
@risc-v: add a specific driver for the JH7110 STG system controller
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.7 2024/11/11 20:01:38 skrll Exp $
d48 5
@


1.7
log
@risc-v: add a JH7110 PCIe PHY driver
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.6 2024/11/11 19:23:18 skrll Exp $
d47 5
@


1.6
log
@risc-v: Add initial JH7110 pin controller driver
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.5 2024/10/26 15:49:43 skrll Exp $
d42 5
@


1.5
log
@risc-v: add ethernet support on JH71[01]0 support

At present only the JH7110 EQOS support is enabled as it work.

The JH7100 has cache coherency issues that need handling before the
gmac can be enabled.
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.4 2024/07/27 07:09:50 skrll Exp $
d27 5
@


1.4
log
@risc-v: split the jh7100 clock controller driver

In preparation for the JH7110 clock driver split the clock definition
and attachment code from the clock handling macros / methods.
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.3 2024/02/07 17:17:59 skrll Exp $
d26 11
@


1.3
log
@risc-v: add a driver the JH7100 pin controller
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.2 2024/01/18 07:48:57 skrll Exp $
d6 1
a6 1
# JH7100 Clock controller
d11 6
@


1.3.2.1
log
@Sync with HEAD
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.11 2025/02/08 16:12:20 skrll Exp $
d6 1
a6 1
# JH71x0 Clock controllers
a10 6
device	jh7110clkc
attach	jh7110clkc at fdt with jh7110_clkc
file	arch/riscv/starfive/jh7110_clkc.c		jh7110_clkc

file	arch/riscv/starfive/jh71x0_clkc.c		jh7100_clkc | jh7110_clkc

a19 41

# JH7100 Pin control
device	jh7110pinctrl
attach	jh7110pinctrl at fdt with jh7110_pinctrl
file	arch/riscv/starfive/jh7110_pinctrl.c		jh7110_pinctrl

# Ethernet
# JH7100 GMAC
attach	awge at fdt with jh7100_gmac

# JH7110 EOQS
attach	eqos at fdt with jh7110_eqos

file	arch/riscv/starfive/jh7100_gmac.c		jh7100_gmac
file	arch/riscv/starfive/jh7110_eqos.c		jh7110_eqos
file	arch/riscv/starfive/jh71x0_eth.c		jh7100_gmac | jh7110_eqos

# JH7110 PCIe PHY
device	jh7110pciephy
attach	jh7110pciephy at fdt with jh7110_pciephy
file	arch/riscv/starfive/jh7110_pciephy.c		jh7110_pciephy

# JH7110 PCIe
device	jh7110pcie: pcibus, pcihost_fdt
attach	jh7110pcie at fdt with jh7110_pcie
file	arch/riscv/starfive/jh7110_pcie.c		jh7110_pcie

# JH7110 system control
device	jh7110syscon
attach	jh7110syscon at fdt with jh7110_syscon
file	arch/riscv/starfive/jh7110_syscon.c		jh7110_syscon

# JH71x0 temperature sensor
device	jh71x0temp
attach	jh71x0temp at fdt with jh71x0_temp
file	arch/riscv/starfive/jh71x0_temp.c		jh71x0_temp

# JH7110 TRNG
device	jh7110trng
attach	jh7110trng at fdt with jh7110_trng
file	arch/riscv/starfive/jh7110_trng.c		jh7110_trng
@


1.2
log
@risc-v: attach the Cadence XHCI usb controller on the JH7100 SoC
@
text
@d1 1
a1 1
#	$NetBSD: files.starfive,v 1.1 2024/01/16 09:06:46 skrll Exp $
d15 5
@


1.1
log
@risc-v: add a StarTech JH7100 SoC clock driver

The JH7100 is seen in the Beagle-V board.
@
text
@d1 1
a1 1
#	$NetBSD$
d11 4
@