head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.4 netbsd-11-0-RC3:1.1.1.4 netbsd-11-0-RC2:1.1.1.4 netbsd-11-0-RC1:1.1.1.4 netbsd-11:1.1.1.4.0.4 netbsd-11-base:1.1.1.4 netbsd-10-1-RELEASE:1.1.1.4 netbsd-9-4-RELEASE:1.1.1.2 netbsd-10-0-RELEASE:1.1.1.4 netbsd-10-0-RC6:1.1.1.4 netbsd-10-0-RC5:1.1.1.4 netbsd-10-0-RC4:1.1.1.4 netbsd-10-0-RC3:1.1.1.4 netbsd-10-0-RC2:1.1.1.4 netbsd-10-0-RC1:1.1.1.4 netbsd-10:1.1.1.4.0.2 netbsd-10-base:1.1.1.4 netbsd-9-3-RELEASE:1.1.1.2 mesa-21-3-7:1.1.1.4 netbsd-9-2-RELEASE:1.1.1.2 netbsd-9-1-RELEASE:1.1.1.2 netbsd-9-0-RELEASE:1.1.1.2 netbsd-9-0-RC2:1.1.1.2 netbsd-9-0-RC1:1.1.1.2 mesalib-19-1-7:1.1.1.3 netbsd-9:1.1.1.2.0.2 netbsd-9-base:1.1.1.2 mesa-18-3-6:1.1.1.2 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.03.10.03.42.47; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.47; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2019.06.01.07.41.09; author mrg; state Exp; branches; next 1.1.1.3; commitid HVa6uub5uYIfqspB; 1.1.1.3 date 2019.09.24.16.42.49; author maya; state Exp; branches; next 1.1.1.4; commitid KJXusGl8fi9AAhEB; 1.1.1.4 date 2022.05.09.01.23.27; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ #include "ir.h" #include "ir_builder.h" #include "ir_rvalue_visitor.h" #include "ir_optimization.h" #include "main/mtypes.h" using namespace ir_builder; namespace { class vector_deref_visitor : public ir_rvalue_enter_visitor { public: vector_deref_visitor() : progress(false) { } virtual ~vector_deref_visitor() { } virtual void handle_rvalue(ir_rvalue **rv); virtual ir_visitor_status visit_enter(ir_assignment *ir); bool progress; }; } /* anonymous namespace */ ir_visitor_status vector_deref_visitor::visit_enter(ir_assignment *ir) { if (!ir->lhs || ir->lhs->ir_type != ir_type_dereference_array) return ir_rvalue_enter_visitor::visit_enter(ir); ir_dereference_array *const deref = (ir_dereference_array *) ir->lhs; if (!deref->array->type->is_vector()) return ir_rvalue_enter_visitor::visit_enter(ir); ir_rvalue *const new_lhs = deref->array; void *mem_ctx = ralloc_parent(ir); ir_constant *old_index_constant = deref->array_index->constant_expression_value(mem_ctx); if (!old_index_constant) { ir->rhs = new(mem_ctx) ir_expression(ir_triop_vector_insert, new_lhs->type, new_lhs->clone(mem_ctx, NULL), ir->rhs, deref->array_index); ir->write_mask = (1 << new_lhs->type->vector_elements) - 1; ir->set_lhs(new_lhs); } else if (new_lhs->ir_type != ir_type_swizzle) { ir->set_lhs(new_lhs); ir->write_mask = 1 << old_index_constant->get_uint_component(0); } else { /* If the "new" LHS is a swizzle, use the set_lhs helper to instead * swizzle the RHS. */ unsigned component[1] = { old_index_constant->get_uint_component(0) }; ir->set_lhs(new(mem_ctx) ir_swizzle(new_lhs, component, 1)); } return ir_rvalue_enter_visitor::visit_enter(ir); } void vector_deref_visitor::handle_rvalue(ir_rvalue **rv) { if (*rv == NULL || (*rv)->ir_type != ir_type_dereference_array) return; ir_dereference_array *const deref = (ir_dereference_array *) *rv; if (!deref->array->type->is_vector()) return; void *mem_ctx = ralloc_parent(deref); *rv = new(mem_ctx) ir_expression(ir_binop_vector_extract, deref->array, deref->array_index); } bool lower_vector_derefs(gl_linked_shader *shader) { vector_deref_visitor v; visit_list_elements(&v, shader->ir); return v.progress; } @ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @initial import of mesa-18.3.6 @ text @d35 2 a36 3 vector_deref_visitor(void *mem_ctx, gl_shader_stage shader_stage) : progress(false), shader_stage(shader_stage), factory(&factory_instructions, mem_ctx) a47 3 gl_shader_stage shader_stage; exec_list factory_instructions; ir_factory factory; d68 7 a74 57 if (shader_stage == MESA_SHADER_TESS_CTRL && deref->variable_referenced()->data.mode == ir_var_shader_out) { /* Tessellation control shader outputs act as if they have memory * backing them and if we have writes from multiple threads * targeting the same vec4 (this can happen for patch outputs), the * load-vec-store pattern of ir_triop_vector_insert doesn't work. * Instead, we have to lower to a series of conditional write-masked * assignments. */ ir_variable *const src_temp = factory.make_temp(ir->rhs->type, "scalar_tmp"); /* The newly created variable declaration goes before the assignment * because we're going to set it as the new LHS. */ ir->insert_before(factory.instructions); ir->set_lhs(new(mem_ctx) ir_dereference_variable(src_temp)); ir_variable *const arr_index = factory.make_temp(deref->array_index->type, "index_tmp"); factory.emit(assign(arr_index, deref->array_index)); for (unsigned i = 0; i < new_lhs->type->vector_elements; i++) { ir_constant *const cmp_index = ir_constant::zero(factory.mem_ctx, deref->array_index->type); cmp_index->value.u[0] = i; ir_rvalue *const lhs_clone = new_lhs->clone(factory.mem_ctx, NULL); ir_dereference_variable *const src_temp_deref = new(mem_ctx) ir_dereference_variable(src_temp); if (new_lhs->ir_type != ir_type_swizzle) { assert(lhs_clone->as_dereference()); ir_assignment *cond_assign = new(mem_ctx) ir_assignment(lhs_clone->as_dereference(), src_temp_deref, equal(arr_index, cmp_index), WRITEMASK_X << i); factory.emit(cond_assign); } else { ir_assignment *cond_assign = new(mem_ctx) ir_assignment(swizzle(lhs_clone, i, 1), src_temp_deref, equal(arr_index, cmp_index)); factory.emit(cond_assign); } } ir->insert_after(factory.instructions); } else { ir->rhs = new(mem_ctx) ir_expression(ir_triop_vector_insert, new_lhs->type, new_lhs->clone(mem_ctx, NULL), ir->rhs, deref->array_index); ir->write_mask = (1 << new_lhs->type->vector_elements) - 1; ir->set_lhs(new_lhs); } d108 1 a108 1 vector_deref_visitor v(shader->ir, shader->Stage); @ 1.1.1.3 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @a65 10 /* SSBOs and shared variables are backed by memory and may be accessed by * multiple threads simultaneously. It's not safe to lower a single * component store to a load-vec-store because it may race with writes to * other components. */ ir_variable *var = deref->variable_referenced(); if (var->data.mode == ir_var_shader_storage || var->data.mode == ir_var_shader_shared) return ir_rvalue_enter_visitor::visit_enter(ir); a152 11 /* Back-ends need to be able to handle derefs on vectors for SSBOs, UBOs, * and shared variables. They have to handle it for writes anyway so we * may as well require it for reads. */ ir_variable *var = deref->variable_referenced(); if (var && (var->data.mode == ir_var_shader_storage || var->data.mode == ir_var_shader_shared || (var->data.mode == ir_var_uniform && var->get_interface_type()))) return; @ 1.1.1.4 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @d139 3 d143 5 a147 24 unsigned index = old_index_constant->get_uint_component(0); if (index >= new_lhs->type->vector_elements) { /* Section 5.11 (Out-of-Bounds Accesses) of the GLSL 4.60 spec says: * * In the subsections described above for array, vector, matrix and * structure accesses, any out-of-bounds access produced undefined * behavior.... Out-of-bounds writes may be discarded or overwrite * other variables of the active program. */ ir->remove(); return visit_continue; } if (new_lhs->ir_type != ir_type_swizzle) { ir->set_lhs(new_lhs); ir->write_mask = 1 << index; } else { /* If the "new" LHS is a swizzle, use the set_lhs helper to instead * swizzle the RHS. */ unsigned component[1] = { index }; ir->set_lhs(new(mem_ctx) ir_swizzle(new_lhs, component, 1)); } @