head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.3 netbsd-11-0-RC3:1.1.1.3 netbsd-11-0-RC2:1.1.1.3 netbsd-11-0-RC1:1.1.1.3 netbsd-11:1.1.1.3.0.4 netbsd-11-base:1.1.1.3 netbsd-10-1-RELEASE:1.1.1.3 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.3 netbsd-10-0-RC6:1.1.1.3 netbsd-10-0-RC5:1.1.1.3 netbsd-10-0-RC4:1.1.1.3 netbsd-10-0-RC3:1.1.1.3 netbsd-10-0-RC2:1.1.1.3 netbsd-10-0-RC1:1.1.1.3 netbsd-10:1.1.1.3.0.2 netbsd-10-base:1.1.1.3 netbsd-9-3-RELEASE:1.1.1.1 mesa-21-3-7:1.1.1.3 netbsd-9-2-RELEASE:1.1.1.1 netbsd-9-1-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 mesalib-19-1-7:1.1.1.2 netbsd-9:1.1.1.1.0.2 netbsd-9-base:1.1.1.1 mesa-18-3-6:1.1.1.1 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2019.09.24.17.39.38; author maya; state Exp; branches; next 1.1.1.3; commitid KJXusGl8fi9AAhEB; 1.1.1.3 date 2022.05.09.01.23.37; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2014 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ #include "brw_fs.h" #include "brw_cfg.h" #include "brw_eu.h" /** @@file brw_fs_cmod_propagation.cpp * * Implements a pass that propagates the conditional modifier from a CMP x 0.0 * instruction into the instruction that generated x. For instance, in this * sequence * * add(8) g70<1>F g69<8,8,1>F 4096F * cmp.ge.f0(8) null g70<8,8,1>F 0F * * we can do the comparison as part of the ADD instruction directly: * * add.ge.f0(8) g70<1>F g69<8,8,1>F 4096F * * If there had been a use of the flag register and another CMP using g70 * * add.ge.f0(8) g70<1>F g69<8,8,1>F 4096F * (+f0) sel(8) g71 g72<8,8,1>F g73<8,8,1>F * cmp.ge.f0(8) null g70<8,8,1>F 0F * * we can recognize that the CMP is generating the flag value that already * exists and therefore remove the instruction. */ static bool cmod_propagate_cmp_to_add(const gen_device_info *devinfo, bblock_t *block, fs_inst *inst) { bool read_flag = false; foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { if (scan_inst->opcode == BRW_OPCODE_ADD && !scan_inst->is_partial_write() && scan_inst->exec_size == inst->exec_size) { bool negate; /* A CMP is basically a subtraction. The result of the * subtraction must be the same as the result of the addition. * This means that one of the operands must be negated. So (a + * b) vs (a == -b) or (a + -b) vs (a == b). */ if ((inst->src[0].equals(scan_inst->src[0]) && inst->src[1].negative_equals(scan_inst->src[1])) || (inst->src[0].equals(scan_inst->src[1]) && inst->src[1].negative_equals(scan_inst->src[0]))) { negate = false; } else if ((inst->src[0].negative_equals(scan_inst->src[0]) && inst->src[1].equals(scan_inst->src[1])) || (inst->src[0].negative_equals(scan_inst->src[1]) && inst->src[1].equals(scan_inst->src[0]))) { negate = true; } else { goto not_match; } /* From the Sky Lake PRM Vol. 7 "Assigning Conditional Mods": * * * Note that the [post condition signal] bits generated at * the output of a compute are before the .sat. * * So we don't have to bail if scan_inst has saturate. */ /* Otherwise, try propagating the conditional. */ const enum brw_conditional_mod cond = negate ? brw_swap_cmod(inst->conditional_mod) : inst->conditional_mod; if (scan_inst->can_do_cmod() && ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) || scan_inst->conditional_mod == cond)) { scan_inst->conditional_mod = cond; inst->remove(block); return true; } break; } not_match: if (scan_inst->flags_written()) break; read_flag = read_flag || scan_inst->flags_read(devinfo); } return false; } /** * Propagate conditional modifiers from NOT instructions * * Attempt to convert sequences like * * or(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD * ... * not.nz.f0(8) null g78<8,8,1>UD * * into * * or.z.f0(8) g78<8,8,1> g76<8,8,1>UD g77<8,8,1>UD */ static bool cmod_propagate_not(const gen_device_info *devinfo, bblock_t *block, fs_inst *inst) { const enum brw_conditional_mod cond = brw_negate_cmod(inst->conditional_mod); bool read_flag = false; if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ) return false; foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) { if (scan_inst->opcode != BRW_OPCODE_OR && scan_inst->opcode != BRW_OPCODE_AND) break; if (scan_inst->is_partial_write() || scan_inst->dst.offset != inst->src[0].offset || scan_inst->exec_size != inst->exec_size) break; if (scan_inst->can_do_cmod() && ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) || scan_inst->conditional_mod == cond)) { scan_inst->conditional_mod = cond; inst->remove(block); return true; } break; } if (scan_inst->flags_written()) break; read_flag = read_flag || scan_inst->flags_read(devinfo); } return false; } static bool opt_cmod_propagation_local(const gen_device_info *devinfo, bblock_t *block) { bool progress = false; int ip = block->end_ip + 1; foreach_inst_in_block_reverse_safe(fs_inst, inst, block) { ip--; if ((inst->opcode != BRW_OPCODE_AND && inst->opcode != BRW_OPCODE_CMP && inst->opcode != BRW_OPCODE_MOV && inst->opcode != BRW_OPCODE_NOT) || inst->predicate != BRW_PREDICATE_NONE || !inst->dst.is_null() || (inst->src[0].file != VGRF && inst->src[0].file != ATTR && inst->src[0].file != UNIFORM)) continue; /* An ABS source modifier can only be handled when processing a compare * with a value other than zero. */ if (inst->src[0].abs && (inst->opcode != BRW_OPCODE_CMP || inst->src[1].is_zero())) continue; /* Only an AND.NZ can be propagated. Many AND.Z instructions are * generated (for ir_unop_not in fs_visitor::emit_bool_to_cond_code). * Propagating those would require inverting the condition on the CMP. * This changes both the flag value and the register destination of the * CMP. That result may be used elsewhere, so we can't change its value * on a whim. */ if (inst->opcode == BRW_OPCODE_AND && !(inst->src[1].is_one() && inst->conditional_mod == BRW_CONDITIONAL_NZ && !inst->src[0].negate)) continue; if (inst->opcode == BRW_OPCODE_MOV && inst->conditional_mod != BRW_CONDITIONAL_NZ) continue; /* A CMP with a second source of zero can match with anything. A CMP * with a second source that is not zero can only match with an ADD * instruction. * * Only apply this optimization to float-point sources. It can fail for * integers. For inputs a = 0x80000000, b = 4, int(0x80000000) < 4, but * int(0x80000000) - 4 overflows and results in 0x7ffffffc. that's not * less than zero, so the flags get set differently than for (a < b). */ if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero()) { if (brw_reg_type_is_floating_point(inst->src[0].type) && cmod_propagate_cmp_to_add(devinfo, block, inst)) progress = true; continue; } if (inst->opcode == BRW_OPCODE_NOT) { progress = cmod_propagate_not(devinfo, block, inst) || progress; continue; } bool read_flag = false; foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) { if (scan_inst->is_partial_write() || scan_inst->dst.offset != inst->src[0].offset || scan_inst->exec_size != inst->exec_size) break; /* CMP's result is the same regardless of dest type. */ if (inst->conditional_mod == BRW_CONDITIONAL_NZ && scan_inst->opcode == BRW_OPCODE_CMP && (inst->dst.type == BRW_REGISTER_TYPE_D || inst->dst.type == BRW_REGISTER_TYPE_UD)) { inst->remove(block); progress = true; break; } /* If the AND wasn't handled by the previous case, it isn't safe * to remove it. */ if (inst->opcode == BRW_OPCODE_AND) break; /* Comparisons operate differently for ints and floats */ if (scan_inst->dst.type != inst->dst.type && (scan_inst->dst.type == BRW_REGISTER_TYPE_F || inst->dst.type == BRW_REGISTER_TYPE_F)) break; /* If the instruction generating inst's source also wrote the * flag, and inst is doing a simple .nz comparison, then inst * is redundant - the appropriate value is already in the flag * register. Delete inst. */ if (inst->conditional_mod == BRW_CONDITIONAL_NZ && !inst->src[0].negate && scan_inst->flags_written()) { inst->remove(block); progress = true; break; } /* The conditional mod of the CMP/CMPN instructions behaves * specially because the flag output is not calculated from the * result of the instruction, but the other way around, which * means that even if the condmod to propagate and the condmod * from the CMP instruction are the same they will in general give * different results because they are evaluated based on different * inputs. */ if (scan_inst->opcode == BRW_OPCODE_CMP || scan_inst->opcode == BRW_OPCODE_CMPN) break; /* From the Sky Lake PRM Vol. 7 "Assigning Conditional Mods": * * * Note that the [post condition signal] bits generated at * the output of a compute are before the .sat. */ if (scan_inst->saturate) break; /* From the Sky Lake PRM, Vol 2a, "Multiply": * * "When multiplying integer data types, if one of the sources * is a DW, the resulting full precision data is stored in * the accumulator. However, if the destination data type is * either W or DW, the low bits of the result are written to * the destination register and the remaining high bits are * discarded. This results in undefined Overflow and Sign * flags. Therefore, conditional modifiers and saturation * (.sat) cannot be used in this case." * * We just disallow cmod propagation on all integer multiplies. */ if (!brw_reg_type_is_floating_point(scan_inst->dst.type) && scan_inst->opcode == BRW_OPCODE_MUL) break; /* Otherwise, try propagating the conditional. */ enum brw_conditional_mod cond = inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod) : inst->conditional_mod; if (scan_inst->can_do_cmod() && ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) || scan_inst->conditional_mod == cond)) { scan_inst->conditional_mod = cond; inst->remove(block); progress = true; } break; } if (scan_inst->flags_written()) break; read_flag = read_flag || scan_inst->flags_read(devinfo); } } return progress; } bool fs_visitor::opt_cmod_propagation() { bool progress = false; foreach_block_reverse(block, cfg) { progress = opt_cmod_propagation_local(devinfo, block) || progress; } if (progress) invalidate_live_intervals(); return progress; } @ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @d245 2 a246 1 brw_reg_type_is_integer(inst->dst.type)) { d258 4 a261 5 /* Not safe to use inequality operators if the types are different */ if (scan_inst->dst.type != inst->src[0].type && inst->conditional_mod != BRW_CONDITIONAL_Z && inst->conditional_mod != BRW_CONDITIONAL_NZ) a263 27 /* Comparisons operate differently for ints and floats */ if (scan_inst->dst.type != inst->dst.type) { /* Comparison result may be altered if the bit-size changes * since that affects range, denorms, etc */ if (type_sz(scan_inst->dst.type) != type_sz(inst->dst.type)) break; /* We should propagate from a MOV to another instruction in a * sequence like: * * and(16) g31<1>UD g20<8,8,1>UD g22<8,8,1>UD * mov.nz.f0(16) null<1>F g31<8,8,1>D */ if (inst->opcode == BRW_OPCODE_MOV) { if ((inst->src[0].type != BRW_REGISTER_TYPE_D && inst->src[0].type != BRW_REGISTER_TYPE_UD) || (scan_inst->dst.type != BRW_REGISTER_TYPE_D && scan_inst->dst.type != BRW_REGISTER_TYPE_UD)) { break; } } else if (brw_reg_type_is_floating_point(scan_inst->dst.type) != brw_reg_type_is_floating_point(inst->dst.type)) { break; } } @ 1.1.1.3 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @a50 2 using namespace brw; d52 1 a52 1 cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block, a55 1 const unsigned flags_written = inst->flags_written(devinfo); d82 1 a82 12 /* If the scan instruction writes a different flag register than the * instruction we're trying to propagate from, bail. * * FINISHME: The second part of the condition may be too strong. * Perhaps (scan_inst->flags_written() & flags_written) != * flags_written? */ if (scan_inst->flags_written(devinfo) != 0 && scan_inst->flags_written(devinfo) != flags_written) goto not_match; /* From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags": d87 1 a87 20 * Paragraph about post_zero does not mention saturation, but * testing it on actual GPUs shows that conditional modifiers * are applied after saturation. * * * post_zero bit: This bit reflects whether the final * result is zero after all the clamping, normalizing, * or format conversion logic. * * For signed types we don't care about saturation: it won't * change the result of conditional modifier. * * For floating and unsigned types there two special cases, * when we can remove inst even if scan_inst is saturated: G * and LE. Since conditional modifiers are just comparations * against zero, saturating positive values to the upper * limit never changes the result of comparation. * * For negative values: * (sat(x) > 0) == (x > 0) --- false * (sat(x) <= 0) == (x <= 0) --- true d89 1 a93 8 if (scan_inst->saturate && (brw_reg_type_is_floating_point(scan_inst->dst.type) || brw_reg_type_is_unsigned_integer(scan_inst->dst.type)) && (cond != BRW_CONDITIONAL_G && cond != BRW_CONDITIONAL_LE)) goto not_match; /* Otherwise, try propagating the conditional. */ d98 1 a98 2 scan_inst->flag_subreg = inst->flag_subreg; inst->remove(block, true); d105 1 a105 1 if ((scan_inst->flags_written(devinfo) & flags_written) != 0) d108 1 a108 2 read_flag = read_flag || (scan_inst->flags_read(devinfo) & flags_written) != 0; d128 1 a128 1 cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block, a132 1 const unsigned flags_written = inst->flags_written(devinfo); a148 11 /* If the scan instruction writes a different flag register than the * instruction we're trying to propagate from, bail. * * FINISHME: The second part of the condition may be too strong. * Perhaps (scan_inst->flags_written() & flags_written) != * flags_written? */ if (scan_inst->flags_written(devinfo) != 0 && scan_inst->flags_written(devinfo) != flags_written) break; d153 1 a153 2 scan_inst->flag_subreg = inst->flag_subreg; inst->remove(block, true); d159 1 a159 1 if ((scan_inst->flags_written(devinfo) & flags_written) != 0) d162 1 a162 2 read_flag = read_flag || (scan_inst->flags_read(devinfo) & flags_written) != 0; d169 1 a169 1 opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) d207 4 a233 1 const unsigned flags_written = inst->flags_written(devinfo); a236 11 /* If the scan instruction writes a different flag register than * the instruction we're trying to propagate from, bail. * * FINISHME: The second part of the condition may be too strong. * Perhaps (scan_inst->flags_written() & flags_written) != * flags_written? */ if (scan_inst->flags_written(devinfo) != 0 && scan_inst->flags_written(devinfo) != flags_written) break; d246 1 a246 1 inst->remove(block, true); d257 6 a262 15 if (inst->opcode == BRW_OPCODE_MOV) { if (brw_reg_type_is_floating_point(scan_inst->dst.type)) { /* If the destination type of scan_inst is floating-point, * then: * * - The source of the MOV instruction must be the same * type. * * - The destination of the MOV instruction must be float * point with a size at least as large as the destination * of inst. Size-reducing f2f conversions could cause * non-zero values to become zero, etc. */ if (scan_inst->dst.type != inst->src[0].type) break; d264 7 a270 2 if (!brw_reg_type_is_floating_point(inst->dst.type)) break; d272 11 a282 1 if (type_sz(scan_inst->dst.type) > type_sz(inst->dst.type)) a283 29 } else { /* If the destination type of scan_inst is integer, then: * * - The source of the MOV instruction must be integer with * the same size. * * - If the conditional modifier is Z or NZ, then the * destination type of inst must either be floating point * (of any size) or integer with a size at least as large * as the destination of inst. * * - If the conditional modifier is neither Z nor NZ, then the * destination type of inst must either be floating point * (of any size) or integer with a size at least as large * as the destination of inst and the same signedness. */ if (!brw_reg_type_is_integer(inst->src[0].type) || type_sz(scan_inst->dst.type) != type_sz(inst->src[0].type)) break; if (brw_reg_type_is_integer(inst->dst.type)) { if (type_sz(inst->dst.type) < type_sz(scan_inst->dst.type)) break; if (inst->conditional_mod != BRW_CONDITIONAL_Z && inst->conditional_mod != BRW_CONDITIONAL_NZ && brw_reg_type_is_unsigned_integer(inst->dst.type) != brw_reg_type_is_unsigned_integer(scan_inst->dst.type)) break; d285 2 a286 8 } } else { /* Not safe to use inequality operators if the types are * different. */ if (scan_inst->dst.type != inst->src[0].type && inst->conditional_mod != BRW_CONDITIONAL_Z && inst->conditional_mod != BRW_CONDITIONAL_NZ) a287 12 /* Comparisons operate differently for ints and floats */ if (scan_inst->dst.type != inst->dst.type) { /* Comparison result may be altered if the bit-size changes * since that affects range, denorms, etc */ if (type_sz(scan_inst->dst.type) != type_sz(inst->dst.type)) break; if (brw_reg_type_is_floating_point(scan_inst->dst.type) != brw_reg_type_is_floating_point(inst->dst.type)) break; d291 4 a294 40 /* Knowing following: * - CMP writes to flag register the result of * applying cmod to the `src0 - src1`. * After that it stores the same value to dst. * Other instructions first store their result to * dst, and then store cmod(dst) to the flag * register. * - inst is either CMP or MOV * - inst->dst is null * - inst->src[0] overlaps with scan_inst->dst * - inst->src[1] is zero * - scan_inst wrote to a flag register * * There can be three possible paths: * * - scan_inst is CMP: * * Considering that src0 is either 0x0 (false), * or 0xffffffff (true), and src1 is 0x0: * * - If inst's cmod is NZ, we can always remove * scan_inst: NZ is invariant for false and true. This * holds even if src0 is NaN: .nz is the only cmod, * that returns true for NaN. * * - .g is invariant if src0 has a UD type * * - .l is invariant if src0 has a D type * * - scan_inst and inst have the same cmod: * * If scan_inst is anything than CMP, it already * wrote the appropriate value to the flag register. * * - else: * * We can change cmod of scan_inst to that of inst, * and remove inst. It is valid as long as we make * sure that no instruction uses the flag register * between scan_inst and inst. d296 6 a301 33 if (!inst->src[0].negate && scan_inst->flags_written(devinfo)) { if (scan_inst->opcode == BRW_OPCODE_CMP) { if ((inst->conditional_mod == BRW_CONDITIONAL_NZ) || (inst->conditional_mod == BRW_CONDITIONAL_G && inst->src[0].type == BRW_REGISTER_TYPE_UD) || (inst->conditional_mod == BRW_CONDITIONAL_L && inst->src[0].type == BRW_REGISTER_TYPE_D)) { inst->remove(block, true); progress = true; break; } } else if (scan_inst->conditional_mod == inst->conditional_mod) { /* On Gfx4 and Gfx5 sel.cond will dirty the flags, but the * flags value is not based on the result stored in the * destination. On all other platforms sel.cond will not * write the flags, so execution will not get to this point. */ if (scan_inst->opcode == BRW_OPCODE_SEL) { assert(devinfo->ver <= 5); } else { inst->remove(block, true); progress = true; } break; } else if (!read_flag && scan_inst->can_do_cmod()) { scan_inst->conditional_mod = inst->conditional_mod; scan_inst->flag_subreg = inst->flag_subreg; inst->remove(block, true); progress = true; break; } d316 8 d341 1 a345 18 /* From the Kaby Lake PRM Vol. 7 "Assigning Conditional Flags": * * * Note that the [post condition signal] bits generated at * the output of a compute are before the .sat. * * Paragraph about post_zero does not mention saturation, but * testing it on actual GPUs shows that conditional modifiers are * applied after saturation. * * * post_zero bit: This bit reflects whether the final * result is zero after all the clamping, normalizing, * or format conversion logic. * * For this reason, no additional restrictions are necessary on * instructions with saturate. */ /* Otherwise, try propagating the conditional. */ d350 1 a350 2 scan_inst->flag_subreg = inst->flag_subreg; inst->remove(block, true); d356 1 a356 1 if ((scan_inst->flags_written(devinfo) & flags_written) != 0) d359 1 a359 2 read_flag = read_flag || (scan_inst->flags_read(devinfo) & flags_written) != 0; a362 3 /* There is progress if and only if instructions were removed. */ assert(progress == (block->end_ip_delta != 0)); d375 2 a376 5 if (progress) { cfg->adjust_block_ips(); invalidate_analysis(DEPENDENCY_INSTRUCTIONS); } @