head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.3 netbsd-11-0-RC3:1.1.1.3 netbsd-11-0-RC2:1.1.1.3 netbsd-11-0-RC1:1.1.1.3 netbsd-11:1.1.1.3.0.4 netbsd-11-base:1.1.1.3 netbsd-10-1-RELEASE:1.1.1.3 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.3 netbsd-10-0-RC6:1.1.1.3 netbsd-10-0-RC5:1.1.1.3 netbsd-10-0-RC4:1.1.1.3 netbsd-10-0-RC3:1.1.1.3 netbsd-10-0-RC2:1.1.1.3 netbsd-10-0-RC1:1.1.1.3 netbsd-10:1.1.1.3.0.2 netbsd-10-base:1.1.1.3 netbsd-9-3-RELEASE:1.1.1.1 mesa-21-3-7:1.1.1.3 netbsd-9-2-RELEASE:1.1.1.1 netbsd-9-1-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 mesalib-19-1-7:1.1.1.2 netbsd-9:1.1.1.1.0.2 netbsd-9-base:1.1.1.1 mesa-18-3-6:1.1.1.1 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2019.09.24.17.40.01; author maya; state Exp; branches; next 1.1.1.3; commitid KJXusGl8fi9AAhEB; 1.1.1.3 date 2022.05.09.01.23.37; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ /** @@file brw_fs_register_coalesce.cpp * * Implements register coalescing: Checks if the two registers involved in a * raw move don't interfere, in which case they can both be stored in the same * place and the MOV removed. * * To do this, all uses of the source of the MOV in the shader are replaced * with the destination of the MOV. For example: * * add vgrf3:F, vgrf1:F, vgrf2:F * mov vgrf4:F, vgrf3:F * mul vgrf5:F, vgrf5:F, vgrf4:F * * becomes * * add vgrf4:F, vgrf1:F, vgrf2:F * mul vgrf5:F, vgrf5:F, vgrf4:F */ #include "brw_fs.h" #include "brw_cfg.h" #include "brw_fs_live_variables.h" static bool is_nop_mov(const fs_inst *inst) { if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { fs_reg dst = inst->dst; for (int i = 0; i < inst->sources; i++) { if (!dst.equals(inst->src[i])) { return false; } dst.offset += (i < inst->header_size ? REG_SIZE : inst->exec_size * dst.stride * type_sz(inst->src[i].type)); } return true; } else if (inst->opcode == BRW_OPCODE_MOV) { return inst->dst.equals(inst->src[0]); } return false; } static bool is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst) { if ((inst->opcode != BRW_OPCODE_MOV && inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) || inst->is_partial_write() || inst->saturate || inst->src[0].file != VGRF || inst->src[0].negate || inst->src[0].abs || !inst->src[0].is_contiguous() || inst->dst.file != VGRF || inst->dst.type != inst->src[0].type) { return false; } if (v->alloc.sizes[inst->src[0].nr] > v->alloc.sizes[inst->dst.nr]) return false; if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { if (!inst->is_copy_payload(v->alloc)) { return false; } } return true; } static bool can_coalesce_vars(brw::fs_live_variables *live_intervals, const cfg_t *cfg, const fs_inst *inst, int dst_var, int src_var) { if (!live_intervals->vars_interfere(src_var, dst_var)) return true; int dst_start = live_intervals->start[dst_var]; int dst_end = live_intervals->end[dst_var]; int src_start = live_intervals->start[src_var]; int src_end = live_intervals->end[src_var]; /* Variables interfere and one line range isn't a subset of the other. */ if ((dst_end > src_end && src_start < dst_start) || (src_end > dst_end && dst_start < src_start)) return false; /* Check for a write to either register in the intersection of their live * ranges. */ int start_ip = MAX2(dst_start, src_start); int end_ip = MIN2(dst_end, src_end); foreach_block(block, cfg) { if (block->end_ip < start_ip) continue; int scan_ip = block->start_ip - 1; foreach_inst_in_block(fs_inst, scan_inst, block) { scan_ip++; /* Ignore anything before the intersection of the live ranges */ if (scan_ip < start_ip) continue; /* Ignore the copying instruction itself */ if (scan_inst == inst) continue; if (scan_ip > end_ip) return true; /* registers do not interfere */ if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->dst, inst->size_written) || regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) return false; /* registers interfere */ } } return true; } bool fs_visitor::register_coalesce() { bool progress = false; calculate_live_intervals(); int src_size = 0; int channels_remaining = 0; int src_reg = -1, dst_reg = -1; int dst_reg_offset[MAX_VGRF_SIZE]; fs_inst *mov[MAX_VGRF_SIZE]; int dst_var[MAX_VGRF_SIZE]; int src_var[MAX_VGRF_SIZE]; foreach_block_and_inst(block, fs_inst, inst, cfg) { if (!is_coalesce_candidate(this, inst)) continue; if (is_nop_mov(inst)) { inst->opcode = BRW_OPCODE_NOP; progress = true; continue; } if (src_reg != inst->src[0].nr) { src_reg = inst->src[0].nr; src_size = alloc.sizes[inst->src[0].nr]; assert(src_size <= MAX_VGRF_SIZE); channels_remaining = src_size; memset(mov, 0, sizeof(mov)); dst_reg = inst->dst.nr; } if (dst_reg != inst->dst.nr) continue; if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { for (int i = 0; i < src_size; i++) { dst_reg_offset[i] = i; } mov[0] = inst; channels_remaining -= regs_written(inst); } else { const int offset = inst->src[0].offset / REG_SIZE; if (mov[offset]) { /* This is the second time that this offset in the register has * been set. This means, in particular, that inst->dst was * live before this instruction and that the live ranges of * inst->dst and inst->src[0] overlap and we can't coalesce the * two variables. Let's ensure that doesn't happen. */ channels_remaining = -1; continue; } for (unsigned i = 0; i < MAX2(inst->size_written / REG_SIZE, 1); i++) dst_reg_offset[offset + i] = inst->dst.offset / REG_SIZE + i; mov[offset] = inst; channels_remaining -= regs_written(inst); } if (channels_remaining) continue; bool can_coalesce = true; for (int i = 0; i < src_size; i++) { if (dst_reg_offset[i] != dst_reg_offset[0] + i) { /* Registers are out-of-order. */ can_coalesce = false; src_reg = -1; break; } dst_var[i] = live_intervals->var_from_vgrf[dst_reg] + dst_reg_offset[i]; src_var[i] = live_intervals->var_from_vgrf[src_reg] + i; if (!can_coalesce_vars(live_intervals, cfg, inst, dst_var[i], src_var[i])) { can_coalesce = false; src_reg = -1; break; } } if (!can_coalesce) continue; progress = true; for (int i = 0; i < src_size; i++) { if (mov[i]) { mov[i]->opcode = BRW_OPCODE_NOP; mov[i]->conditional_mod = BRW_CONDITIONAL_NONE; mov[i]->dst = reg_undef; for (int j = 0; j < mov[i]->sources; j++) { mov[i]->src[j] = reg_undef; } } } foreach_block_and_inst(block, fs_inst, scan_inst, cfg) { if (scan_inst->dst.file == VGRF && scan_inst->dst.nr == src_reg) { scan_inst->dst.nr = dst_reg; scan_inst->dst.offset = scan_inst->dst.offset % REG_SIZE + dst_reg_offset[scan_inst->dst.offset / REG_SIZE] * REG_SIZE; } for (int j = 0; j < scan_inst->sources; j++) { if (scan_inst->src[j].file == VGRF && scan_inst->src[j].nr == src_reg) { scan_inst->src[j].nr = dst_reg; scan_inst->src[j].offset = scan_inst->src[j].offset % REG_SIZE + dst_reg_offset[scan_inst->src[j].offset / REG_SIZE] * REG_SIZE; } } } for (int i = 0; i < src_size; i++) { live_intervals->start[dst_var[i]] = MIN2(live_intervals->start[dst_var[i]], live_intervals->start[src_var[i]]); live_intervals->end[dst_var[i]] = MAX2(live_intervals->end[dst_var[i]], live_intervals->end[src_var[i]]); } src_reg = -1; } if (progress) { foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) { if (inst->opcode == BRW_OPCODE_NOP) { inst->remove(block); } } invalidate_live_intervals(); } return progress; } @ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @d161 1 a161 1 unsigned src_reg = ~0u, dst_reg = ~0u; d224 1 a224 1 src_reg = ~0u; d234 1 a234 1 src_reg = ~0u; d281 1 a281 1 src_reg = ~0u; @ 1.1.1.3 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @a46 2 using namespace brw; d89 1 a89 1 if (!is_coalescing_payload(v->alloc, inst)) { d98 2 a99 2 can_coalesce_vars(const fs_live_variables &live, const cfg_t *cfg, const bblock_t *block, const fs_inst *inst, d102 1 a102 1 if (!live.vars_interfere(src_var, dst_var)) d105 4 a108 4 int dst_start = live.start[dst_var]; int dst_end = live.end[dst_var]; int src_start = live.start[src_var]; int src_end = live.end[src_var]; d121 2 a122 2 foreach_block(scan_block, cfg) { if (scan_block->end_ip < start_ip) d125 1 a125 1 int scan_ip = scan_block->start_ip - 1; d127 1 a127 3 bool seen_src_write = false; bool seen_copy = false; foreach_inst_in_block(fs_inst, scan_inst, scan_block) { d135 1 a135 2 if (scan_inst == inst) { seen_copy = true; a136 1 } a140 26 if (seen_src_write && !seen_copy) { /* In order to satisfy the guarantee of register coalescing, we * must ensure that the two registers always have the same value * during the intersection of their live ranges. One way to do * this is to simply ensure that neither is ever written apart * from the one copy which syncs up the two registers. However, * this can be overly conservative and only works in the case * where the destination live range is entirely contained in the * source live range. * * To handle the other case where the source is contained in the * destination, we allow writes to the source register as long as * they happen before the copy, in the same block as the copy, and * the destination is never read between first such write and the * copy. This effectively moves the write from the copy up. */ for (int j = 0; j < scan_inst->sources; j++) { if (regions_overlap(scan_inst->src[j], scan_inst->size_read(j), inst->dst, inst->size_written)) return false; /* registers interfere */ } } /* The MOV being coalesced had better be the only instruction which * writes to the coalesce destination in the intersection. */ d142 3 a144 1 inst->dst, inst->size_written)) a145 8 /* See the big comment above */ if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(0))) { if (seen_copy || scan_block != block) return false; seen_src_write = true; } d156 3 a158 1 fs_live_variables &live = live_analysis.require(); d228 2 a229 2 dst_var[i] = live.var_from_vgrf[dst_reg] + dst_reg_offset[i]; src_var[i] = live.var_from_vgrf[src_reg] + i; d231 2 a232 1 if (!can_coalesce_vars(live, cfg, block, inst, dst_var[i], src_var[i])) { d245 1 a245 4 if (!mov[i]) continue; if (mov[i]->conditional_mod == BRW_CONDITIONAL_NONE) { d247 1 a251 11 } else { /* If we have a conditional modifier, rewrite the MOV to be a * MOV.cmod from the coalesced register. Hopefully, cmod * propagation will clean this up and move it to the instruction * that writes the register. If not, this keeps things correct * while still letting us coalesce. */ assert(mov[i]->opcode == BRW_OPCODE_MOV); assert(mov[i]->sources == 1); mov[i]->src[0] = mov[i]->dst; mov[i]->dst = retype(brw_null_reg(), mov[i]->dst.type); d274 6 a279 4 live.start[dst_var[i]] = MIN2(live.start[dst_var[i]], live.start[src_var[i]]); live.end[dst_var[i]] = MAX2(live.end[dst_var[i]], live.end[src_var[i]]); d287 1 a287 1 inst->remove(block, true); d291 1 a291 3 cfg->adjust_block_ips(); invalidate_analysis(DEPENDENCY_INSTRUCTIONS); @