head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.3 netbsd-11-0-RC3:1.1.1.3 netbsd-11-0-RC2:1.1.1.3 netbsd-11-0-RC1:1.1.1.3 netbsd-11:1.1.1.3.0.4 netbsd-11-base:1.1.1.3 netbsd-10-1-RELEASE:1.1.1.3 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.3 netbsd-10-0-RC6:1.1.1.3 netbsd-10-0-RC5:1.1.1.3 netbsd-10-0-RC4:1.1.1.3 netbsd-10-0-RC3:1.1.1.3 netbsd-10-0-RC2:1.1.1.3 netbsd-10-0-RC1:1.1.1.3 netbsd-10:1.1.1.3.0.2 netbsd-10-base:1.1.1.3 netbsd-9-3-RELEASE:1.1.1.1 mesa-21-3-7:1.1.1.3 netbsd-9-2-RELEASE:1.1.1.1 netbsd-9-1-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 mesalib-19-1-7:1.1.1.2 netbsd-9:1.1.1.1.0.2 netbsd-9-base:1.1.1.1 mesa-18-3-6:1.1.1.1 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2019.09.24.17.41.09; author maya; state Exp; branches; next 1.1.1.3; commitid KJXusGl8fi9AAhEB; 1.1.1.3 date 2022.05.09.01.23.37; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ /** * \file brw_vec4_tcs.cpp * * Tessellaton control shader specific code derived from the vec4_visitor class. */ #include "brw_nir.h" #include "brw_vec4_tcs.h" #include "brw_fs.h" #include "common/gen_debug.h" namespace brw { vec4_tcs_visitor::vec4_tcs_visitor(const struct brw_compiler *compiler, void *log_data, const struct brw_tcs_prog_key *key, struct brw_tcs_prog_data *prog_data, const nir_shader *nir, void *mem_ctx, int shader_time_index, const struct brw_vue_map *input_vue_map) : vec4_visitor(compiler, log_data, &key->tex, &prog_data->base, nir, mem_ctx, false, shader_time_index), input_vue_map(input_vue_map), key(key) { } void vec4_tcs_visitor::setup_payload() { int reg = 0; /* The payload always contains important data in r0, which contains * the URB handles that are passed on to the URB write at the end * of the thread. */ reg++; /* r1.0 - r4.7 may contain the input control point URB handles, * which we use to pull vertex data. */ reg += 4; /* Push constants may start at r5.0 */ reg = setup_uniforms(reg); this->first_non_payload_grf = reg; } void vec4_tcs_visitor::emit_prolog() { invocation_id = src_reg(this, glsl_type::uint_type); emit(TCS_OPCODE_GET_INSTANCE_ID, dst_reg(invocation_id)); /* HS threads are dispatched with the dispatch mask set to 0xFF. * If there are an odd number of output vertices, then the final * HS instance dispatched will only have its bottom half doing real * work, and so we need to disable the upper half: */ if (nir->info.tess.tcs_vertices_out % 2) { emit(CMP(dst_null_d(), invocation_id, brw_imm_ud(nir->info.tess.tcs_vertices_out), BRW_CONDITIONAL_L)); /* Matching ENDIF is in emit_thread_end() */ emit(IF(BRW_PREDICATE_NORMAL)); } } void vec4_tcs_visitor::emit_thread_end() { vec4_instruction *inst; current_annotation = "thread end"; if (nir->info.tess.tcs_vertices_out % 2) { emit(BRW_OPCODE_ENDIF); } if (devinfo->gen == 7) { struct brw_tcs_prog_data *tcs_prog_data = (struct brw_tcs_prog_data *) prog_data; current_annotation = "release input vertices"; /* Synchronize all threads, so we know that no one is still * using the input URB handles. */ if (tcs_prog_data->instances > 1) { dst_reg header = dst_reg(this, glsl_type::uvec4_type); emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header); emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header)); } /* Make thread 0 (invocations <1, 0>) release pairs of ICP handles. * We want to compare the bottom half of invocation_id with 0, but * use that truth value for the top half as well. Unfortunately, * we don't have stride in the vec4 world, nor UV immediates in * align16, so we need an opcode to get invocation_id<0,4,0>. */ set_condmod(BRW_CONDITIONAL_Z, emit(TCS_OPCODE_SRC0_010_IS_ZERO, dst_null_d(), invocation_id)); emit(IF(BRW_PREDICATE_NORMAL)); for (unsigned i = 0; i < key->input_vertices; i += 2) { /* If we have an odd number of input vertices, the last will be * unpaired. We don't want to use an interleaved URB write in * that case. */ const bool is_unpaired = i == key->input_vertices - 1; dst_reg header(this, glsl_type::uvec4_type); emit(TCS_OPCODE_RELEASE_INPUT, header, brw_imm_ud(i), brw_imm_ud(is_unpaired)); } emit(BRW_OPCODE_ENDIF); } if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME)) emit_shader_time_end(); inst = emit(TCS_OPCODE_THREAD_END); inst->base_mrf = 14; inst->mlen = 2; } void vec4_tcs_visitor::emit_input_urb_read(const dst_reg &dst, const src_reg &vertex_index, unsigned base_offset, unsigned first_component, const src_reg &indirect_offset) { vec4_instruction *inst; dst_reg temp(this, glsl_type::ivec4_type); temp.type = dst.type; /* Set up the message header to reference the proper parts of the URB */ dst_reg header = dst_reg(this, glsl_type::uvec4_type); inst = emit(TCS_OPCODE_SET_INPUT_URB_OFFSETS, header, vertex_index, indirect_offset); inst->force_writemask_all = true; /* Read into a temporary, ignoring writemasking. */ inst = emit(VEC4_OPCODE_URB_READ, temp, src_reg(header)); inst->offset = base_offset; inst->mlen = 1; inst->base_mrf = -1; /* Copy the temporary to the destination to deal with writemasking. * * Also attempt to deal with gl_PointSize being in the .w component. */ if (inst->offset == 0 && indirect_offset.file == BAD_FILE) { emit(MOV(dst, swizzle(src_reg(temp), BRW_SWIZZLE_WWWW))); } else { src_reg src = src_reg(temp); src.swizzle = BRW_SWZ_COMP_INPUT(first_component); emit(MOV(dst, src)); } } void vec4_tcs_visitor::emit_output_urb_read(const dst_reg &dst, unsigned base_offset, unsigned first_component, const src_reg &indirect_offset) { vec4_instruction *inst; /* Set up the message header to reference the proper parts of the URB */ dst_reg header = dst_reg(this, glsl_type::uvec4_type); inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, header, brw_imm_ud(dst.writemask << first_component), indirect_offset); inst->force_writemask_all = true; vec4_instruction *read = emit(VEC4_OPCODE_URB_READ, dst, src_reg(header)); read->offset = base_offset; read->mlen = 1; read->base_mrf = -1; if (first_component) { /* Read into a temporary and copy with a swizzle and writemask. */ read->dst = retype(dst_reg(this, glsl_type::ivec4_type), dst.type); emit(MOV(dst, swizzle(src_reg(read->dst), BRW_SWZ_COMP_INPUT(first_component)))); } } void vec4_tcs_visitor::emit_urb_write(const src_reg &value, unsigned writemask, unsigned base_offset, const src_reg &indirect_offset) { if (writemask == 0) return; src_reg message(this, glsl_type::uvec4_type, 2); vec4_instruction *inst; inst = emit(TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, dst_reg(message), brw_imm_ud(writemask), indirect_offset); inst->force_writemask_all = true; inst = emit(MOV(byte_offset(dst_reg(retype(message, value.type)), REG_SIZE), value)); inst->force_writemask_all = true; inst = emit(TCS_OPCODE_URB_WRITE, dst_null_f(), message); inst->offset = base_offset; inst->mlen = 2; inst->base_mrf = -1; } void vec4_tcs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr) { switch (instr->intrinsic) { case nir_intrinsic_load_invocation_id: emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD), invocation_id)); break; case nir_intrinsic_load_primitive_id: emit(TCS_OPCODE_GET_PRIMITIVE_ID, get_nir_dest(instr->dest, BRW_REGISTER_TYPE_UD)); break; case nir_intrinsic_load_patch_vertices_in: emit(MOV(get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D), brw_imm_d(key->input_vertices))); break; case nir_intrinsic_load_per_vertex_input: { src_reg indirect_offset = get_indirect_offset(instr); unsigned imm_offset = instr->const_index[0]; nir_const_value *vertex_const = nir_src_as_const_value(instr->src[0]); src_reg vertex_index = vertex_const ? src_reg(brw_imm_ud(vertex_const->u32[0])) : get_nir_src(instr->src[0], BRW_REGISTER_TYPE_UD, 1); unsigned first_component = nir_intrinsic_component(instr); if (nir_dest_bit_size(instr->dest) == 64) { /* We need to emit up to two 32-bit URB reads, then shuffle * the result into a temporary, then move to the destination * honoring the writemask * * We don't need to divide first_component by 2 because * emit_input_urb_read takes a 32-bit type. */ dst_reg tmp = dst_reg(this, glsl_type::dvec4_type); dst_reg tmp_d = retype(tmp, BRW_REGISTER_TYPE_D); emit_input_urb_read(tmp_d, vertex_index, imm_offset, first_component, indirect_offset); if (instr->num_components > 2) { emit_input_urb_read(byte_offset(tmp_d, REG_SIZE), vertex_index, imm_offset + 1, 0, indirect_offset); } src_reg tmp_src = retype(src_reg(tmp_d), BRW_REGISTER_TYPE_DF); dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type); shuffle_64bit_data(shuffled, tmp_src, false); dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_DF); dst.writemask = brw_writemask_for_size(instr->num_components); emit(MOV(dst, src_reg(shuffled))); } else { dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); dst.writemask = brw_writemask_for_size(instr->num_components); emit_input_urb_read(dst, vertex_index, imm_offset, first_component, indirect_offset); } break; } case nir_intrinsic_load_input: unreachable("nir_lower_io should use load_per_vertex_input intrinsics"); break; case nir_intrinsic_load_output: case nir_intrinsic_load_per_vertex_output: { src_reg indirect_offset = get_indirect_offset(instr); unsigned imm_offset = instr->const_index[0]; dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); dst.writemask = brw_writemask_for_size(instr->num_components); emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr), indirect_offset); break; } case nir_intrinsic_store_output: case nir_intrinsic_store_per_vertex_output: { src_reg value = get_nir_src(instr->src[0]); unsigned mask = instr->const_index[1]; unsigned swiz = BRW_SWIZZLE_XYZW; src_reg indirect_offset = get_indirect_offset(instr); unsigned imm_offset = instr->const_index[0]; unsigned first_component = nir_intrinsic_component(instr); if (first_component) { if (nir_src_bit_size(instr->src[0]) == 64) first_component /= 2; assert(swiz == BRW_SWIZZLE_XYZW); swiz = BRW_SWZ_COMP_OUTPUT(first_component); mask = mask << first_component; } if (nir_src_bit_size(instr->src[0]) == 64) { /* For 64-bit data we need to shuffle the data before we write and * emit two messages. Also, since each channel is twice as large we * need to fix the writemask in each 32-bit message to account for it. */ value = swizzle(retype(value, BRW_REGISTER_TYPE_DF), swiz); dst_reg shuffled = dst_reg(this, glsl_type::dvec4_type); shuffle_64bit_data(shuffled, value, true); src_reg shuffled_float = src_reg(retype(shuffled, BRW_REGISTER_TYPE_F)); for (int n = 0; n < 2; n++) { unsigned fixed_mask = 0; if (mask & WRITEMASK_X) fixed_mask |= WRITEMASK_XY; if (mask & WRITEMASK_Y) fixed_mask |= WRITEMASK_ZW; emit_urb_write(shuffled_float, fixed_mask, imm_offset, indirect_offset); shuffled_float = byte_offset(shuffled_float, REG_SIZE); mask >>= 2; imm_offset++; } } else { emit_urb_write(swizzle(value, swiz), mask, imm_offset, indirect_offset); } break; } case nir_intrinsic_barrier: { dst_reg header = dst_reg(this, glsl_type::uvec4_type); emit(TCS_OPCODE_CREATE_BARRIER_HEADER, header); emit(SHADER_OPCODE_BARRIER, dst_null_ud(), src_reg(header)); break; } default: vec4_visitor::nir_emit_intrinsic(instr); } } extern "C" const unsigned * brw_compile_tcs(const struct brw_compiler *compiler, void *log_data, void *mem_ctx, const struct brw_tcs_prog_key *key, struct brw_tcs_prog_data *prog_data, const nir_shader *src_shader, int shader_time_index, char **error_str) { const struct gen_device_info *devinfo = compiler->devinfo; struct brw_vue_prog_data *vue_prog_data = &prog_data->base; const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL]; const unsigned *assembly; nir_shader *nir = nir_shader_clone(mem_ctx, src_shader); nir->info.outputs_written = key->outputs_written; nir->info.patch_outputs_written = key->patch_outputs_written; struct brw_vue_map input_vue_map; brw_compute_vue_map(devinfo, &input_vue_map, nir->info.inputs_read, nir->info.separate_shader); brw_compute_tess_vue_map(&vue_prog_data->vue_map, nir->info.outputs_written, nir->info.patch_outputs_written); nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar); brw_nir_lower_vue_inputs(nir, &input_vue_map); brw_nir_lower_tcs_outputs(nir, &vue_prog_data->vue_map, key->tes_primitive_mode); if (key->quads_workaround) brw_nir_apply_tcs_quads_workaround(nir); nir = brw_postprocess_nir(nir, compiler, is_scalar); if (is_scalar) prog_data->instances = DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, 8); else prog_data->instances = DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, 2); /* Compute URB entry size. The maximum allowed URB entry size is 32k. * That divides up as follows: * * 32 bytes for the patch header (tessellation factors) * 480 bytes for per-patch varyings (a varying component is 4 bytes and * gl_MaxTessPatchComponents = 120) * 16384 bytes for per-vertex varyings (a varying component is 4 bytes, * gl_MaxPatchVertices = 32 and * gl_MaxTessControlOutputComponents = 128) * * 15808 bytes left for varying packing overhead */ const int num_per_patch_slots = vue_prog_data->vue_map.num_per_patch_slots; const int num_per_vertex_slots = vue_prog_data->vue_map.num_per_vertex_slots; unsigned output_size_bytes = 0; /* Note that the patch header is counted in num_per_patch_slots. */ output_size_bytes += num_per_patch_slots * 16; output_size_bytes += nir->info.tess.tcs_vertices_out * num_per_vertex_slots * 16; assert(output_size_bytes >= 1); if (output_size_bytes > GEN7_MAX_HS_URB_ENTRY_SIZE_BYTES) return NULL; /* URB entry sizes are stored as a multiple of 64 bytes. */ vue_prog_data->urb_entry_size = ALIGN(output_size_bytes, 64) / 64; /* On Cannonlake software shall not program an allocation size that * specifies a size that is a multiple of 3 64B (512-bit) cachelines. */ if (devinfo->gen == 10 && vue_prog_data->urb_entry_size % 3 == 0) vue_prog_data->urb_entry_size++; /* HS does not use the usual payload pushing from URB to GRFs, * because we don't have enough registers for a full-size payload, and * the hardware is broken on Haswell anyway. */ vue_prog_data->urb_read_length = 0; if (unlikely(INTEL_DEBUG & DEBUG_TCS)) { fprintf(stderr, "TCS Input "); brw_print_vue_map(stderr, &input_vue_map); fprintf(stderr, "TCS Output "); brw_print_vue_map(stderr, &vue_prog_data->vue_map); } if (is_scalar) { fs_visitor v(compiler, log_data, mem_ctx, (void *) key, &prog_data->base.base, NULL, nir, 8, shader_time_index, &input_vue_map); if (!v.run_tcs_single_patch()) { if (error_str) *error_str = ralloc_strdup(mem_ctx, v.fail_msg); return NULL; } prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs; prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8; fs_generator g(compiler, log_data, mem_ctx, &prog_data->base.base, v.promoted_constants, false, MESA_SHADER_TESS_CTRL); if (unlikely(INTEL_DEBUG & DEBUG_TCS)) { g.enable_debug(ralloc_asprintf(mem_ctx, "%s tessellation control shader %s", nir->info.label ? nir->info.label : "unnamed", nir->info.name)); } g.generate_code(v.cfg, 8); assembly = g.get_assembly(); } else { vec4_tcs_visitor v(compiler, log_data, key, prog_data, nir, mem_ctx, shader_time_index, &input_vue_map); if (!v.run()) { if (error_str) *error_str = ralloc_strdup(mem_ctx, v.fail_msg); return NULL; } if (unlikely(INTEL_DEBUG & DEBUG_TCS)) v.dump_instructions(); assembly = brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir, &prog_data->base, v.cfg); } return assembly; } } /* namespace brw */ @ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @d33 1 a33 1 #include "dev/gen_debug.h" d263 4 a266 2 src_reg vertex_index = retype(get_nir_src_imm(instr->src[0]), BRW_REGISTER_TYPE_UD); d383 1 a383 1 nir_shader *nir, d392 1 @ 1.1.1.3 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @d33 1 a33 1 #include "dev/intel_debug.h" d44 4 a47 4 bool debug_enabled) : vec4_visitor(compiler, log_data, &key->base.tex, &prog_data->base, nir, mem_ctx, false, shader_time_index, debug_enabled), key(key) d107 1 a107 1 if (devinfo->ver == 7) { d146 1 a146 1 if (INTEL_DEBUG(DEBUG_SHADER_TIME)) a259 1 assert(nir_dest_bit_size(instr->dest) == 32); d267 30 a296 4 dst_reg dst = get_nir_dest(instr->dest, BRW_REGISTER_TYPE_D); dst.writemask = brw_writemask_for_size(instr->num_components); emit_input_urb_read(dst, vertex_index, imm_offset, first_component, indirect_offset); a315 1 assert(nir_src_bit_size(instr->src[0]) == 32); d325 2 d332 27 a358 2 emit_urb_write(swizzle(value, swiz), mask, imm_offset, indirect_offset); d362 1 a362 1 case nir_intrinsic_control_barrier: { a368 3 case nir_intrinsic_memory_barrier_tcs_patch: break; a373 30 /** * Return the number of patches to accumulate before an 8_PATCH mode thread is * launched. In cases with a large number of input control points and a large * amount of VS outputs, the VS URB space needed to store an entire 8 patches * worth of data can be prohibitive, so it can be beneficial to launch threads * early. * * See the 3DSTATE_HS::Patch Count Threshold documentation for the recommended * values. Note that 0 means to "disable" early dispatch, meaning to wait for * a full 8 patches as normal. */ static int get_patch_count_threshold(int input_control_points) { if (input_control_points <= 4) return 0; else if (input_control_points <= 6) return 5; else if (input_control_points <= 8) return 4; else if (input_control_points <= 10) return 3; else if (input_control_points <= 14) return 2; /* Return patch count 1 for PATCHLIST_15 - PATCHLIST_32 */ return 1; } } /* namespace brw */ a382 1 struct brw_compile_stats *stats, d385 1 a385 1 const struct intel_device_info *devinfo = compiler->devinfo; a387 1 const bool debug_enabled = INTEL_DEBUG(DEBUG_TCS); a389 2 vue_prog_data->base.stage = MESA_SHADER_TESS_CTRL; d395 1 a395 1 nir->info.separate_shader, 1); d400 1 a400 1 brw_nir_apply_key(nir, compiler, &key->base, 8, is_scalar); d407 1 a407 7 brw_postprocess_nir(nir, compiler, is_scalar, debug_enabled, key->base.robust_buffer_access); bool has_primitive_id = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID); prog_data->patch_count_threshold = brw::get_patch_count_threshold(key->input_vertices); d409 4 a412 18 if (compiler->use_tcs_8_patch && nir->info.tess.tcs_vertices_out <= (devinfo->ver >= 12 ? 32 : 16) && 2 + has_primitive_id + key->input_vertices <= (devinfo->ver >= 12 ? 63 : 31)) { /* 3DSTATE_HS imposes two constraints on using 8_PATCH mode. First, the * "Instance" field limits the number of output vertices to [1, 16] on * gfx11 and below, or [1, 32] on gfx12 and above. Secondly, the * "Dispatch GRF Start Register for URB Data" field is limited to [0, * 31] - which imposes a limit on the input vertices. */ vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_8_PATCH; prog_data->instances = nir->info.tess.tcs_vertices_out; prog_data->include_primitive_id = has_primitive_id; } else { unsigned verts_per_thread = is_scalar ? 8 : 2; vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_SINGLE_PATCH; prog_data->instances = DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, verts_per_thread); } d435 1 a435 1 if (output_size_bytes > GFX7_MAX_HS_URB_ENTRY_SIZE_BYTES) d441 7 d454 1 a454 1 if (unlikely(debug_enabled)) { d456 1 a456 1 brw_print_vue_map(stderr, &input_vue_map, MESA_SHADER_TESS_CTRL); d458 1 a458 1 brw_print_vue_map(stderr, &vue_prog_data->vue_map, MESA_SHADER_TESS_CTRL); d462 4 a465 4 fs_visitor v(compiler, log_data, mem_ctx, &key->base, &prog_data->base.base, nir, 8, shader_time_index, debug_enabled); if (!v.run_tcs()) { d472 1 d475 3 a477 2 &prog_data->base.base, false, MESA_SHADER_TESS_CTRL); if (unlikely(debug_enabled)) { d485 1 a485 4 g.generate_code(v.cfg, 8, v.shader_stats, v.performance_analysis.require(), stats); g.add_const_data(nir->constant_data, nir->constant_data_size); d489 2 a490 3 brw::vec4_tcs_visitor v(compiler, log_data, key, prog_data, nir, mem_ctx, shader_time_index, debug_enabled); d497 1 a497 1 if (INTEL_DEBUG(DEBUG_TCS)) d502 1 a502 3 &prog_data->base, v.cfg, v.performance_analysis.require(), stats, debug_enabled); d507 3 @