head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.2 netbsd-11-0-RC3:1.1.1.2 netbsd-11-0-RC2:1.1.1.2 netbsd-11-0-RC1:1.1.1.2 netbsd-11:1.1.1.2.0.4 netbsd-11-base:1.1.1.2 netbsd-10-1-RELEASE:1.1.1.2 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.2 netbsd-10-0-RC6:1.1.1.2 netbsd-10-0-RC5:1.1.1.2 netbsd-10-0-RC4:1.1.1.2 netbsd-10-0-RC3:1.1.1.2 netbsd-10-0-RC2:1.1.1.2 netbsd-10-0-RC1:1.1.1.2 netbsd-10:1.1.1.2.0.2 netbsd-10-base:1.1.1.2 netbsd-9-3-RELEASE:1.1.1.1 mesa-21-3-7:1.1.1.2 netbsd-9-2-RELEASE:1.1.1.1 netbsd-9-1-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 mesalib-19-1-7:1.1.1.1 netbsd-9:1.1.1.1.0.2 netbsd-9-base:1.1.1.1 mesa-18-3-6:1.1.1.1 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2022.05.09.01.23.37; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ #include #include #include #include "util/ralloc.h" #include "brw_eu.h" static bool test_compact_instruction(struct brw_codegen *p, brw_inst src) { brw_compact_inst dst; memset(&dst, 0xd0, sizeof(dst)); if (brw_try_compact_instruction(p->devinfo, &dst, &src)) { brw_inst uncompacted; brw_uncompact_instruction(p->devinfo, &uncompacted, &dst); if (memcmp(&uncompacted, &src, sizeof(src))) { brw_debug_compact_uncompact(p->devinfo, &src, &uncompacted); return false; } } else { brw_compact_inst unchanged; memset(&unchanged, 0xd0, sizeof(unchanged)); /* It's not supposed to change dst unless it compacted. */ if (memcmp(&unchanged, &dst, sizeof(dst))) { fprintf(stderr, "Failed to compact, but dst changed\n"); fprintf(stderr, " Instruction: "); brw_disassemble_inst(stderr, p->devinfo, &src, false); return false; } } return true; } /** * When doing fuzz testing, pad bits won't round-trip. * * This sort of a superset of skip_bit, which is testing for changing bits that * aren't worth testing for fuzzing. We also just want to clear bits that * become meaningless once fuzzing twiddles a related bit. */ static void clear_pad_bits(const struct gen_device_info *devinfo, brw_inst *inst) { if (brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SEND && brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SENDC && brw_inst_src0_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE && brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) { brw_inst_set_bits(inst, 127, 111, 0); } if (devinfo->gen == 8 && !devinfo->is_cherryview && is_3src(devinfo, (opcode)brw_inst_opcode(devinfo, inst))) { brw_inst_set_bits(inst, 105, 105, 0); brw_inst_set_bits(inst, 84, 84, 0); brw_inst_set_bits(inst, 36, 35, 0); } } static bool skip_bit(const struct gen_device_info *devinfo, brw_inst *src, int bit) { /* pad bit */ if (bit == 7) return true; /* The compact bit -- uncompacted can't have it set. */ if (bit == 29) return true; if (is_3src(devinfo, (opcode)brw_inst_opcode(devinfo, src))) { if (devinfo->gen >= 9 || devinfo->is_cherryview) { if (bit == 127) return true; } else { if (bit >= 126 && bit <= 127) return true; if (bit == 105) return true; if (bit == 84) return true; if (bit >= 35 && bit <= 36) return true; } } else { if (bit == 47) return true; if (devinfo->gen >= 8) { if (bit == 11) return true; if (bit == 95) return true; } else { if (devinfo->gen < 7 && bit == 90) return true; if (bit >= 91 && bit <= 95) return true; } } /* sometimes these are pad bits. */ if (brw_inst_opcode(devinfo, src) != BRW_OPCODE_SEND && brw_inst_opcode(devinfo, src) != BRW_OPCODE_SENDC && brw_inst_src0_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE && brw_inst_src1_reg_file(devinfo, src) != BRW_IMMEDIATE_VALUE && bit >= 121) { return true; } return false; } static bool test_fuzz_compact_instruction(struct brw_codegen *p, brw_inst src) { for (int bit0 = 0; bit0 < 128; bit0++) { if (skip_bit(p->devinfo, &src, bit0)) continue; for (int bit1 = 0; bit1 < 128; bit1++) { brw_inst instr = src; uint64_t *bits = instr.data; if (skip_bit(p->devinfo, &src, bit1)) continue; bits[bit0 / 64] ^= (1ull << (bit0 & 63)); bits[bit1 / 64] ^= (1ull << (bit1 & 63)); clear_pad_bits(p->devinfo, &instr); if (!test_compact_instruction(p, instr)) { printf(" twiddled bits for fuzzing %d, %d\n", bit0, bit1); return false; } } } return true; } static void gen_ADD_GRF_GRF_GRF(struct brw_codegen *p) { struct brw_reg g0 = brw_vec8_grf(0, 0); struct brw_reg g2 = brw_vec8_grf(2, 0); struct brw_reg g4 = brw_vec8_grf(4, 0); brw_ADD(p, g0, g2, g4); } static void gen_ADD_GRF_GRF_IMM(struct brw_codegen *p) { struct brw_reg g0 = brw_vec8_grf(0, 0); struct brw_reg g2 = brw_vec8_grf(2, 0); brw_ADD(p, g0, g2, brw_imm_f(1.0)); } static void gen_ADD_GRF_GRF_IMM_d(struct brw_codegen *p) { struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D); struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D); brw_ADD(p, g0, g2, brw_imm_d(1)); } static void gen_MOV_GRF_GRF(struct brw_codegen *p) { struct brw_reg g0 = brw_vec8_grf(0, 0); struct brw_reg g2 = brw_vec8_grf(2, 0); brw_MOV(p, g0, g2); } static void gen_ADD_MRF_GRF_GRF(struct brw_codegen *p) { struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0); struct brw_reg g2 = brw_vec8_grf(2, 0); struct brw_reg g4 = brw_vec8_grf(4, 0); brw_ADD(p, m6, g2, g4); } static void gen_ADD_vec1_GRF_GRF_GRF(struct brw_codegen *p) { struct brw_reg g0 = brw_vec1_grf(0, 0); struct brw_reg g2 = brw_vec1_grf(2, 0); struct brw_reg g4 = brw_vec1_grf(4, 0); brw_ADD(p, g0, g2, g4); } static void gen_PLN_MRF_GRF_GRF(struct brw_codegen *p) { struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0); struct brw_reg interp = brw_vec1_grf(2, 0); struct brw_reg g4 = brw_vec8_grf(4, 0); brw_PLN(p, m6, interp, g4); } static void gen_f0_0_MOV_GRF_GRF(struct brw_codegen *p) { struct brw_reg g0 = brw_vec8_grf(0, 0); struct brw_reg g2 = brw_vec8_grf(2, 0); brw_push_insn_state(p); brw_set_default_predicate_control(p, true); brw_MOV(p, g0, g2); brw_pop_insn_state(p); } /* The handling of f0.1 vs f0.0 changes between gen6 and gen7. Explicitly test * it, so that we run the fuzzing can run over all the other bits that might * interact with it. */ static void gen_f0_1_MOV_GRF_GRF(struct brw_codegen *p) { struct brw_reg g0 = brw_vec8_grf(0, 0); struct brw_reg g2 = brw_vec8_grf(2, 0); brw_push_insn_state(p); brw_set_default_predicate_control(p, true); brw_inst *mov = brw_MOV(p, g0, g2); brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1); brw_pop_insn_state(p); } struct { void (*func)(struct brw_codegen *p); } tests[] = { { gen_MOV_GRF_GRF }, { gen_ADD_GRF_GRF_GRF }, { gen_ADD_GRF_GRF_IMM }, { gen_ADD_GRF_GRF_IMM_d }, { gen_ADD_MRF_GRF_GRF }, { gen_ADD_vec1_GRF_GRF_GRF }, { gen_PLN_MRF_GRF_GRF }, { gen_f0_0_MOV_GRF_GRF }, { gen_f0_1_MOV_GRF_GRF }, }; static bool run_tests(const struct gen_device_info *devinfo) { brw_init_compaction_tables(devinfo); bool fail = false; for (unsigned i = 0; i < ARRAY_SIZE(tests); i++) { for (int align_16 = 0; align_16 <= 1; align_16++) { struct brw_codegen *p = rzalloc(NULL, struct brw_codegen); brw_init_codegen(devinfo, p, p); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); if (align_16) brw_set_default_access_mode(p, BRW_ALIGN_16); else brw_set_default_access_mode(p, BRW_ALIGN_1); tests[i].func(p); assert(p->nr_insn == 1); if (!test_compact_instruction(p, p->store[0])) { fail = true; continue; } if (!test_fuzz_compact_instruction(p, p->store[0])) { fail = true; continue; } ralloc_free(p); } } return fail; } int main(int argc, char **argv) { struct gen_device_info *devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo)); bool fail = false; for (devinfo->gen = 5; devinfo->gen <= 9; devinfo->gen++) { fail |= run_tests(devinfo); } return fail; } @ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @a29 26 #include struct CompactParams { unsigned verx10; unsigned align; }; std::string get_compact_params_name(const testing::TestParamInfo p) { CompactParams params = p.param; std::stringstream ss; ss << params.verx10 << "_"; switch (params.align) { case BRW_ALIGN_1: ss << "Align_1"; break; case BRW_ALIGN_16: ss << "Align_16"; break; default: unreachable("invalid align"); } return ss.str(); } d51 1 a51 1 brw_disassemble_inst(stderr, p->devinfo, &src, false, 0, NULL); d67 1 a67 1 clear_pad_bits(const struct intel_device_info *devinfo, brw_inst *inst) d76 2 a77 2 if (devinfo->ver == 8 && !devinfo->is_cherryview && is_3src(devinfo, brw_inst_opcode(devinfo, inst))) { d85 1 a85 1 skip_bit(const struct intel_device_info *devinfo, brw_inst *src, int bit) d95 2 a96 2 if (is_3src(devinfo, brw_inst_opcode(devinfo, src))) { if (devinfo->ver >= 9 || devinfo->is_cherryview) { d116 1 a116 1 if (devinfo->ver >= 8) { d123 1 a123 1 if (devinfo->ver < 7 && bit == 90) a161 3 if (!brw_validate_instruction(p->devinfo, &instr, 0, NULL)) continue; d172 2 a173 60 class CompactTestFixture : public testing::TestWithParam { protected: virtual void SetUp() { CompactParams params = GetParam(); mem_ctx = ralloc_context(NULL); devinfo = rzalloc(mem_ctx, intel_device_info); p = rzalloc(mem_ctx, brw_codegen); devinfo->verx10 = params.verx10; devinfo->ver = devinfo->verx10 / 10; brw_init_codegen(devinfo, p, p); brw_set_default_predicate_control(p, BRW_PREDICATE_NONE); brw_set_default_access_mode(p, params.align); }; virtual void TearDown() { EXPECT_EQ(p->nr_insn, 1); EXPECT_TRUE(test_compact_instruction(p, p->store[0])); EXPECT_TRUE(test_fuzz_compact_instruction(p, p->store[0])); ralloc_free(mem_ctx); }; void *mem_ctx; intel_device_info *devinfo; brw_codegen *p; }; class Instructions : public CompactTestFixture {}; INSTANTIATE_TEST_CASE_P( CompactTest, Instructions, testing::Values( CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 }, CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 }, CompactParams{ 70, BRW_ALIGN_1 }, CompactParams{ 70, BRW_ALIGN_16 }, CompactParams{ 75, BRW_ALIGN_1 }, CompactParams{ 75, BRW_ALIGN_16 }, CompactParams{ 80, BRW_ALIGN_1 }, CompactParams{ 80, BRW_ALIGN_16 }, CompactParams{ 90, BRW_ALIGN_1 }, CompactParams{ 90, BRW_ALIGN_16 }, CompactParams{ 110, BRW_ALIGN_1 }, CompactParams{ 120, BRW_ALIGN_1 }, CompactParams{ 125, BRW_ALIGN_1 } ), get_compact_params_name); class InstructionsBeforeIvyBridge : public CompactTestFixture {}; INSTANTIATE_TEST_CASE_P( CompactTest, InstructionsBeforeIvyBridge, testing::Values( CompactParams{ 50, BRW_ALIGN_1 }, CompactParams{ 50, BRW_ALIGN_16 }, CompactParams{ 60, BRW_ALIGN_1 }, CompactParams{ 60, BRW_ALIGN_16 } ), get_compact_params_name); TEST_P(Instructions, ADD_GRF_GRF_GRF) d182 2 a183 1 TEST_P(Instructions, ADD_GRF_GRF_IMM) d191 2 a192 1 TEST_P(Instructions, ADD_GRF_GRF_IMM_d) d200 2 a201 1 TEST_P(Instructions, MOV_GRF_GRF) d209 2 a210 1 TEST_P(InstructionsBeforeIvyBridge, ADD_MRF_GRF_GRF) d219 2 a220 1 TEST_P(Instructions, ADD_vec1_GRF_GRF_GRF) d229 2 a230 1 TEST_P(InstructionsBeforeIvyBridge, PLN_MRF_GRF_GRF) d239 2 a240 1 TEST_P(Instructions, f0_0_MOV_GRF_GRF) d246 1 a246 1 brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); d251 1 a251 1 /* The handling of f0.1 vs f0.0 changes between gfx6 and gfx7. Explicitly test d255 2 a256 1 TEST_P(Instructions, f0_1_MOV_GRF_GRF) d262 1 a262 1 brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL); d267 64 @