head 1.1; branch 1.1.1; access; symbols netbsd-11-0-RC4:1.1.1.3 netbsd-11-0-RC3:1.1.1.3 netbsd-11-0-RC2:1.1.1.3 netbsd-11-0-RC1:1.1.1.3 netbsd-11:1.1.1.3.0.4 netbsd-11-base:1.1.1.3 netbsd-10-1-RELEASE:1.1.1.3 netbsd-9-4-RELEASE:1.1.1.1 netbsd-10-0-RELEASE:1.1.1.3 netbsd-10-0-RC6:1.1.1.3 netbsd-10-0-RC5:1.1.1.3 netbsd-10-0-RC4:1.1.1.3 netbsd-10-0-RC3:1.1.1.3 netbsd-10-0-RC2:1.1.1.3 netbsd-10-0-RC1:1.1.1.3 netbsd-10:1.1.1.3.0.2 netbsd-10-base:1.1.1.3 netbsd-9-3-RELEASE:1.1.1.1 mesa-21-3-7:1.1.1.3 netbsd-9-2-RELEASE:1.1.1.1 netbsd-9-1-RELEASE:1.1.1.1 netbsd-9-0-RELEASE:1.1.1.1 netbsd-9-0-RC2:1.1.1.1 netbsd-9-0-RC1:1.1.1.1 mesalib-19-1-7:1.1.1.2 netbsd-9:1.1.1.1.0.2 netbsd-9-base:1.1.1.1 mesa-18-3-6:1.1.1.1 mesa-18-3-4:1.1.1.1 xorg:1.1.1; locks; strict; comment @// @; 1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches 1.1.1.1; next ; commitid r12jo1Nf3ebQKLeB; 1.1.1.1 date 2019.03.10.03.42.41; author mrg; state Exp; branches; next 1.1.1.2; commitid r12jo1Nf3ebQKLeB; 1.1.1.2 date 2019.09.24.17.41.19; author maya; state Exp; branches; next 1.1.1.3; commitid KJXusGl8fi9AAhEB; 1.1.1.3 date 2022.05.09.01.23.37; author mrg; state Exp; branches; next ; commitid UEBs6hNk81DdQjDD; desc @@ 1.1 log @Initial revision @ text @/* * Copyright © 2015 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. */ #include #include "brw_fs.h" #include "brw_cfg.h" #include "program/program.h" using namespace brw; class cmod_propagation_test : public ::testing::Test { virtual void SetUp(); public: struct brw_compiler *compiler; struct gen_device_info *devinfo; struct gl_context *ctx; struct brw_wm_prog_data *prog_data; struct gl_shader_program *shader_prog; fs_visitor *v; }; class cmod_propagation_fs_visitor : public fs_visitor { public: cmod_propagation_fs_visitor(struct brw_compiler *compiler, struct brw_wm_prog_data *prog_data, nir_shader *shader) : fs_visitor(compiler, NULL, NULL, NULL, &prog_data->base, (struct gl_program *) NULL, shader, 8, -1) {} }; void cmod_propagation_test::SetUp() { ctx = (struct gl_context *)calloc(1, sizeof(*ctx)); compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler)); devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo)); compiler->devinfo = devinfo; prog_data = ralloc(NULL, struct brw_wm_prog_data); nir_shader *shader = nir_shader_create(NULL, MESA_SHADER_FRAGMENT, NULL, NULL); v = new cmod_propagation_fs_visitor(compiler, prog_data, shader); devinfo->gen = 4; } static fs_inst * instruction(bblock_t *block, int num) { fs_inst *inst = (fs_inst *)block->start(); for (int i = 0; i < num; i++) { inst = (fs_inst *)inst->next; } return inst; } static bool cmod_propagation(fs_visitor *v) { const bool print = getenv("TEST_DEBUG"); if (print) { fprintf(stderr, "= Before =\n"); v->cfg->dump(v); } bool ret = v->opt_cmod_propagation(); if (print) { fprintf(stderr, "\n= After =\n"); v->cfg->dump(v); } return ret; } TEST_F(cmod_propagation_test, basic) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest src0 src1 * 1: cmp.ge.f0(8) null dest 0.0f * * = After = * 0: add.ge.f0(8) dest src0 src1 */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_nonzero) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg nonzero(brw_imm_f(1.0f)); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), dest, nonzero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest src0 src1 * 1: cmp.ge.f0(8) null dest 1.0f * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, non_cmod_instruction) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::uint_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg zero(brw_imm_ud(0u)); bld.FBL(dest, src0); bld.CMP(bld.null_reg_ud(), dest, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: fbl(8) dest src0 * 1: cmp.ge.f0(8) null dest 0u * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_FBL, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, intervening_flag_write) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE); bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest src0 src1 * 1: cmp.ge.f0(8) null src2 0.0f * 2: cmp.ge.f0(8) null dest 0.0f * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, intervening_flag_read) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest0, src0, src1); set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); bld.CMP(bld.null_reg_f(), dest0, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest0 src0 src1 * 1: (+f0) sel(8) dest1 src2 0.0f * 2: cmp.ge.f0(8) null dest0 0.0f * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, intervening_dest_write) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::vec4_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::vec2_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(offset(dest, bld, 2), src0, src1); bld.emit(SHADER_OPCODE_TEX, dest, src2) ->size_written = 4 * REG_SIZE; bld.CMP(bld.null_reg_f(), offset(dest, bld, 2), zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest+2 src0 src1 * 1: tex(8) rlen 4 dest+0 src2 * 2: cmp.ge.f0(8) null dest+2 0.0f * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(SHADER_OPCODE_TEX, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, intervening_flag_read_same_value) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); set_condmod(BRW_CONDITIONAL_GE, bld.ADD(dest0, src0, src1)); set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); bld.CMP(bld.null_reg_f(), dest0, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add.ge.f0(8) dest0 src0 src1 * 1: (+f0) sel(8) dest1 src2 0.0f * 2: cmp.ge.f0(8) null dest0 0.0f * * = After = * 0: add.ge.f0(8) dest0 src0 src1 * 1: (+f0) sel(8) dest1 src2 0.0f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, negate) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest, src0, src1); dest.negate = true; bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest src0 src1 * 1: cmp.ge.f0(8) null -dest 0.0f * * = After = * 0: add.le.f0(8) dest src0 src1 */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, movnz) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.CMP(dest, src0, src1, BRW_CONDITIONAL_GE); set_condmod(BRW_CONDITIONAL_NZ, bld.MOV(bld.null_reg_f(), dest)); /* = Before = * * 0: cmp.ge.f0(8) dest src0 src1 * 1: mov.nz.f0(8) null dest * * = After = * 0: cmp.ge.f0(8) dest src0 src1 */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, different_types_cmod_with_zero) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::int_type); fs_reg src0 = v->vgrf(glsl_type::int_type); fs_reg src1 = v->vgrf(glsl_type::int_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), retype(dest, BRW_REGISTER_TYPE_F), zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest:D src0:D src1:D * 1: cmp.ge.f0(8) null:F dest:F 0.0f * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, andnz_one) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::int_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); fs_reg one(brw_imm_d(1)); bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); set_condmod(BRW_CONDITIONAL_NZ, bld.AND(bld.null_reg_d(), dest, one)); /* = Before = * 0: cmp.l.f0(8) dest:F src0:F 0F * 1: and.nz.f0(8) null:D dest:D 1D * * = After = * 0: cmp.l.f0(8) dest:F src0:F 0F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_TRUE(retype(dest, BRW_REGISTER_TYPE_F) .equals(instruction(block0, 0)->dst)); } TEST_F(cmod_propagation_test, andnz_non_one) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::int_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); fs_reg nonone(brw_imm_d(38)); bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); set_condmod(BRW_CONDITIONAL_NZ, bld.AND(bld.null_reg_d(), dest, nonone)); /* = Before = * 0: cmp.l.f0(8) dest:F src0:F 0F * 1: and.nz.f0(8) null:D dest:D 38D * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, andz_one) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::int_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); fs_reg one(brw_imm_d(1)); bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); set_condmod(BRW_CONDITIONAL_Z, bld.AND(bld.null_reg_d(), dest, one)); /* = Before = * 0: cmp.l.f0(8) dest:F src0:F 0F * 1: and.z.f0(8) null:D dest:D 1D * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, add_not_merge_with_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* The addition and the implicit subtraction in the compare do not compute * related values. * * = Before = * 0: add(8) dest:F src0:F src1:F * 1: cmp.l.f0(8) null:F src0:F src1:F * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_merge_with_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest, src0, negate(src1)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add(8) dest:F src0:F -src1:F * 1: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.l.f0(8) dest:F src0:F -src1:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_immediate_merge_with_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg one(brw_imm_f(1.0f)); fs_reg negative_one(brw_imm_f(-1.0f)); bld.ADD(dest, src0, negative_one); bld.CMP(bld.null_reg_f(), src0, one, BRW_CONDITIONAL_NZ); /* = Before = * 0: add(8) dest:F src0:F -1.0f * 1: cmp.nz.f0(8) null:F src0:F 1.0f * * = After = * 0: add.nz.f0(8) dest:F src0:F -1.0f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_add) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest0, src0, negate(src1)); bld.ADD(dest1, src0, src1); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F * 1: add(8) dest1:F src0:F src1:F * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: add(8) dest1:F src0:F src1:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_partial_write) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest0, src0, negate(src1)); set_predicate(BRW_PREDICATE_NORMAL, bld.ADD(dest1, src0, negate(src1))); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F * 1: (+f0) add(8) dest1:F src0:F -src1:F * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 1)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_add) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest0, src0, negate(src1)); set_condmod(BRW_CONDITIONAL_EQ, bld.ADD(dest1, src0, src1)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F * 1: add.z.f0(8) dest1:F src0:F src1:F * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, add_merge_with_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), src0, negate(src1), BRW_CONDITIONAL_L); /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: cmp.l.f0(8) null:F src0:F -src1:F * * = After = * 0: add.l.f0(8) dest:F src0:F src1:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, negative_subtract_merge_with_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest, src1, negate(src0)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* The result of the subtract is the negatiion of the result of the * implicit subtract in the compare, so the condition must change. * * = Before = * 0: add(8) dest:F src1:F -src0:F * 1: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.g.f0(8) dest:F src0:F -src1:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_delete_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))); set_predicate(BRW_PREDICATE_NORMAL, bld.MOV(dest1, src2)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: (+f0) mov(0) dest1:F src2:F * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.l.f0(8) dest:F src0:F -src1:F * 1: (+f0) mov(0) dest1:F src2:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, subtract_delete_compare_derp) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest0, src0, negate(src1))); set_predicate(BRW_PREDICATE_NORMAL, bld.ADD(dest1, negate(src0), src1)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: (+f0) add(0) dest1:F -src0:F src1:F * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: (+f0) add(0) dest1:F -src0:F src1:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } @ 1.1.1.1 log @from maya: Import mesa 18.3.4. Mesa 18.3.4 implements the OpenGL 4.5 API. Some drivers don't support all the features required in OpenGL 4.5. @ text @@ 1.1.1.2 log @Import mesa 19.1.7 New features in mesa 19.1.0: GL_ARB_parallel_shader_compile on all drivers. GL_EXT_gpu_shader4 on all GL 3.1 drivers. GL_EXT_shader_image_load_formatted on radeonsi. GL_EXT_texture_buffer_object on all GL 3.1 drivers. GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension). GL_NV_compute_shader_derivatives on iris and i965. GL_KHR_parallel_shader_compile on all drivers. VK_EXT_buffer_device_address on Intel and RADV. VK_EXT_depth_clip_enable on Intel and RADV. VK_KHR_ycbcr_image_arrays on Intel. VK_EXT_inline_uniform_block on Intel and RADV. VK_EXT_external_memory_host on Intel. VK_EXT_host_query_reset on Intel and RADV. VK_KHR_surface_protected_capabilities on Intel and RADV. VK_EXT_pipeline_creation_feedback on Intel and RADV. VK_KHR_8bit_storage on RADV. VK_AMD_gpu_shader_int16 on RADV. VK_AMD_gpu_shader_half_float on RADV. VK_NV_compute_shader_derivatives on Intel. VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8). VK_KHR_shader_atomic_int64 on Intel. VK_EXT_descriptor_indexing on Intel. VK_KHR_shader_float16_int8 on Intel and RADV. GL_INTEL_conservative_rasterization on iris. VK_EXT_memory_budget on Intel. New features in mesa 19.0.0: GL_AMD_texture_texture4 on all GL 4.0 drivers. GL_EXT_shader_implicit_conversions on all drivers (ES extension). GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension). GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension). GL_EXT_render_snorm on gallium drivers (ES extension). GL_EXT_texture_view on drivers supporting texture views (ES extension). GL_OES_texture_view on drivers supporting texture views (ES extension). GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only). Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965. VK_ANDROID_external_memory_android_hardware_buffer on Intel Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV VK_EXT_scalar_block_layout on Intel and RADV VK_KHR_depth_stencil_resolve on Intel VK_KHR_draw_indirect_count on Intel VK_EXT_conditional_rendering on Intel VK_EXT_memory_budget on RADV Also, bug fixes. @ text @d68 1 a68 1 devinfo->gen = 7; a891 32 TEST_F(cmod_propagation_test, signed_unsigned_comparison_mismatch) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::int_type); fs_reg src0 = v->vgrf(glsl_type::int_type); src0.type = BRW_REGISTER_TYPE_W; bld.ASR(dest0, negate(src0), brw_imm_d(15)); bld.CMP(bld.null_reg_ud(), retype(dest0, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u), BRW_CONDITIONAL_LE); /* = Before = * 0: asr(8) dest:D -src0:W 15D * 1: cmp.le.f0(8) null:UD dest:UD 0UD * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ASR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 1)->conditional_mod); } @ 1.1.1.3 log @initial import of mesa 21.3.7 main changes since 19.1.7 include: - more support for Vulkan functions - better supported for newer radeonsi (both amdgpu and radeon backends) - various bug fixes in many drivers - many fixes and enhancements for intel drivers - some fixes for nvidia - OpenGL 4.6 for some drivers (intel, radeonsi) - intel Tigerlake and Rocketlake support - Vulkan 1.2 for some drivers - OpenGL 4.5, GLES 3.2, and more on llvmpipe - working Panfrost and Midgard drivers - fix warnings in radeonsi vs newer llvm @ text @a32 1 virtual void TearDown(); d36 2 a37 2 struct intel_device_info *devinfo; void *ctx; a40 11 void test_mov_prop(enum brw_conditional_mod cmod, enum brw_reg_type add_type, enum brw_reg_type mov_dst_type, bool expected_cmod_prop_progress); void test_saturate_prop(enum brw_conditional_mod before, enum opcode op, enum brw_reg_type add_type, enum brw_reg_type op_type, bool expected_cmod_prop_progress); a46 1 void *mem_ctx, d49 3 a51 2 : fs_visitor(compiler, NULL, mem_ctx, NULL, &prog_data->base, shader, 8, -1, false) {} d57 3 a59 3 ctx = ralloc_context(NULL); compiler = rzalloc(ctx, struct brw_compiler); devinfo = rzalloc(ctx, struct intel_device_info); d62 1 a62 1 prog_data = ralloc(ctx, struct brw_wm_prog_data); d64 1 a64 7 nir_shader_create(ctx, MESA_SHADER_FRAGMENT, NULL, NULL); v = new cmod_propagation_fs_visitor(compiler, ctx, prog_data, shader); devinfo->ver = 7; devinfo->verx10 = devinfo->ver * 10; } d66 1 a66 4 void cmod_propagation_test::TearDown() { delete v; v = NULL; d68 1 a68 2 ralloc_free(ctx); ctx = NULL; d88 1 a88 1 v->cfg->dump(); d95 1 a95 1 v->cfg->dump(); a132 34 TEST_F(cmod_propagation_test, basic_other_flag) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE) ->flag_subreg = 1; /* = Before = * * 0: add(8) dest src0 src1 * 1: cmp.ge.f0.1(8) null dest 0.0f * * = After = * 0: add.ge.f0.1(8) dest src0 src1 */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(1, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); } a197 32 TEST_F(cmod_propagation_test, non_cmod_livechannel) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::uint_type); fs_reg zero(brw_imm_d(0)); bld.emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, dest)->exec_size = 32; bld.CMP(bld.null_reg_d(), dest, zero, BRW_CONDITIONAL_Z)->exec_size = 32; /* = Before = * * 0: find_live_channel(32) dest * 1: cmp.z.f0.0(32) null dest 0d * * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(SHADER_OPCODE_FIND_LIVE_CHANNEL, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 1)->conditional_mod); } a235 41 TEST_F(cmod_propagation_test, intervening_mismatch_flag_write) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), src2, zero, BRW_CONDITIONAL_GE) ->flag_subreg = 1; bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest src0 src1 * 1: cmp.ge.f0.1(8) null src2 0.0f * 2: cmp.ge.f0(8) null dest 0.0f * * = After = * 0: add.ge.f0(8) dest src0 src1 * 1: cmp.ge.f0.1(8) null src2 0.0f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } a274 42 TEST_F(cmod_propagation_test, intervening_mismatch_flag_read) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest0, src0, src1); set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) ->flag_subreg = 1; bld.CMP(bld.null_reg_f(), dest0, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest0 src0 src1 * 1: (+f0.1) sel(8) dest1 src2 0.0f * 2: cmp.ge.f0(8) null dest0 0.0f * * = After = * 0: add.ge.f0(8) dest0 src0 src1 * 1: (+f0.1) sel(8) dest1 src2 0.0f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } d523 1 a523 1 TEST_F(cmod_propagation_test, cmp_cmpnz) d526 1 a526 2 fs_reg dst0 = v->vgrf(glsl_type::float_type); d528 2 a529 1 fs_reg zero(brw_imm_f(0)); d531 3 a533 2 bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_NZ); d536 2 a537 2 * 0: cmp.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f * 1: cmp.nz.f0.0(8) null:F, vgrf0:F, 0f d540 1 a540 1 * 0: cmp.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f a545 1 EXPECT_TRUE(cmod_propagation(v)); d547 5 a551 1 EXPECT_EQ(0, block0->end_ip); d553 3 a555 1 EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); d558 1 a558 1 TEST_F(cmod_propagation_test, cmp_cmpg) d561 1 a561 2 fs_reg dst0 = v->vgrf(glsl_type::float_type); d563 3 a565 1 fs_reg zero(brw_imm_f(0)); d567 6 a572 6 bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_G); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f * 1: cmp.g.f0.0(8) null:F, vgrf0:F, 0f a576 1 d580 3 d586 2 a587 2 EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); d589 1 a589 1 EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 1)->conditional_mod); d592 1 a592 1 TEST_F(cmod_propagation_test, plnnz_cmpnz) d595 1 a595 2 fs_reg dst0 = v->vgrf(glsl_type::float_type); d597 3 a599 4 fs_reg zero(brw_imm_f(0)); set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_NZ); d602 2 a603 2 * 0: pln.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f * 1: cmp.nz.f0.0(8) null:F, vgrf0:F, 0f d606 1 a606 1 * 0: pln.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f a607 1 d611 3 d617 2 a618 2 EXPECT_EQ(BRW_OPCODE_PLN, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); d621 1 a621 1 TEST_F(cmod_propagation_test, plnnz_cmpz) d624 1 a624 2 fs_reg dst0 = v->vgrf(glsl_type::float_type); d626 2 a627 1 fs_reg zero(brw_imm_f(0)); d629 2 a630 2 set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_Z); d633 2 a634 2 * 0: pln.nz.f0.0(8) vgrf0:F, vgrf1:F, 0f * 1: cmp.z.f0.0(8) null:F, vgrf0:F, 0f d637 1 a637 1 * 0: pln.z.f0.0(8) vgrf0:F, vgrf1:F, 0f a638 1 d642 3 d648 2 a649 2 EXPECT_EQ(BRW_OPCODE_PLN, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); d652 1 a652 1 TEST_F(cmod_propagation_test, plnnz_sel_cmpz) d655 2 a656 3 fs_reg dst0 = v->vgrf(glsl_type::float_type); fs_reg dst1 = v->vgrf(glsl_type::float_type); d658 4 a661 5 fs_reg zero(brw_imm_f(0)); set_condmod(BRW_CONDITIONAL_NZ, bld.PLN(dst0, src0, zero)); set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dst1, src0, zero)); bld.CMP(bld.null_reg_f(), dst0, zero, BRW_CONDITIONAL_Z); d664 3 a666 3 * 0: pln.nz.f0.0(8) vgrf0:F, vgrf2:F, 0f * 1: (+f0.0) sel(8) vgrf1:F, vgrf2:F, 0f * 2: cmp.z.f0.0(8) null:F, vgrf0:F, 0f d669 2 a670 1 * (no changes) a671 1 a674 1 EXPECT_FALSE(cmod_propagation(v)); d677 8 a684 6 EXPECT_EQ(BRW_OPCODE_PLN, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 2)->conditional_mod); d687 1 a687 1 TEST_F(cmod_propagation_test, cmp_cmpg_D) d690 7 a696 8 fs_reg dst0 = v->vgrf(glsl_type::int_type); fs_reg src0 = v->vgrf(glsl_type::int_type); fs_reg zero(brw_imm_d(0)); fs_reg one(brw_imm_d(1)); bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); bld.CMP(bld.null_reg_d(), dst0, zero, BRW_CONDITIONAL_G); d699 3 a701 2 * 0: cmp.nz.f0.0(8) vgrf0:D, vgrf1:D, 0d * 1: cmp.g.f0.0(8) null:D, vgrf0:D, 0d a705 1 d709 3 d714 7 a720 5 EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 1)->conditional_mod); d723 1 a723 1 TEST_F(cmod_propagation_test, cmp_cmpg_UD) d726 2 a727 90 fs_reg dst0 = v->vgrf(glsl_type::uint_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg zero(brw_imm_ud(0)); bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); bld.CMP(bld.null_reg_ud(), dst0, zero, BRW_CONDITIONAL_G); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:UD, vgrf1:UD, 0u * 1: cmp.g.f0.0(8) null:UD, vgrf0:UD, 0u * * = After = * 0: cmp.nz.f0.0(8) vgrf0:UD, vgrf1:UD, 0u */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_cmpl_D) { const fs_builder &bld = v->bld; fs_reg dst0 = v->vgrf(glsl_type::int_type); fs_reg src0 = v->vgrf(glsl_type::int_type); fs_reg zero(brw_imm_d(0)); bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); bld.CMP(bld.null_reg_d(), dst0, zero, BRW_CONDITIONAL_L); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:D, vgrf1:D, 0d * 1: cmp.l.f0.0(8) null:D, vgrf0:D, 0d * * = After = * 0: cmp.nz.f0.0(8) vgrf0:D, vgrf1:D, 0d */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_cmpl_UD) { const fs_builder &bld = v->bld; fs_reg dst0 = v->vgrf(glsl_type::uint_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg zero(brw_imm_ud(0)); bld.CMP(dst0, src0, zero, BRW_CONDITIONAL_NZ); bld.CMP(bld.null_reg_ud(), dst0, zero, BRW_CONDITIONAL_L); /* = Before = * 0: cmp.nz.f0.0(8) vgrf0:UD, vgrf1:UD, 0u * 1: cmp.l.f0.0(8) null:UD, vgrf0:UD, 0u * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, andz_one) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::int_type); d729 4 a732 6 fs_reg zero(brw_imm_f(0.0f)); fs_reg one(brw_imm_d(1)); bld.CMP(retype(dest, BRW_REGISTER_TYPE_F), src0, zero, BRW_CONDITIONAL_L); set_condmod(BRW_CONDITIONAL_Z, bld.AND(bld.null_reg_d(), dest, one)); d735 3 a737 2 * 0: cmp.l.f0(8) dest:F src0:F 0F * 1: and.z.f0(8) null:D dest:D 1D a741 1 d746 1 a746 1 EXPECT_EQ(1, block0->end_ip); d750 4 a753 4 EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 1)->opcode); d755 2 d759 1 a759 1 TEST_F(cmod_propagation_test, add_not_merge_with_compare) d766 1 a766 1 bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); d768 1 a768 4 /* The addition and the implicit subtraction in the compare do not compute * related values. * * = Before = d770 1 a770 1 * 1: cmp.l.f0(8) null:F src0:F src1:F d773 1 a773 1 * (no changes) d781 1 a781 1 EXPECT_FALSE(cmod_propagation(v)); d783 1 a783 1 EXPECT_EQ(1, block0->end_ip); d785 1 a785 3 EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); d788 1 a788 1 TEST_F(cmod_propagation_test, subtract_merge_with_compare) d794 1 a794 1 bld.ADD(dest, src0, negate(src1)); d797 5 a801 2 /* = Before = * 0: add(8) dest:F src0:F -src1:F d805 1 a805 1 * 0: add.l.f0(8) dest:F src0:F -src1:F d817 1 a817 1 EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); d820 1 a820 1 TEST_F(cmod_propagation_test, subtract_immediate_merge_with_compare) a823 31 fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg one(brw_imm_f(1.0f)); fs_reg negative_one(brw_imm_f(-1.0f)); bld.ADD(dest, src0, negative_one); bld.CMP(bld.null_reg_f(), src0, one, BRW_CONDITIONAL_NZ); /* = Before = * 0: add(8) dest:F src0:F -1.0f * 1: cmp.nz.f0(8) null:F src0:F 1.0f * * = After = * 0: add.nz.f0(8) dest:F src0:F -1.0f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_add) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); d827 4 a830 2 bld.ADD(dest0, src0, negate(src1)); bld.ADD(dest1, src0, src1); d834 2 a835 2 * 0: add(8) dest0:F src0:F -src1:F * 1: add(8) dest1:F src0:F src1:F d839 2 a840 2 * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: add(8) dest1:F src0:F src1:F d853 2 a854 2 EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 1)->conditional_mod); d857 1 a857 1 TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_partial_write) d864 3 a866 2 bld.ADD(dest0, src0, negate(src1)); set_predicate(BRW_PREDICATE_NORMAL, bld.ADD(dest1, src0, negate(src1))); d870 2 a871 2 * 0: add(8) dest0:F src0:F -src1:F * 1: (+f0) add(8) dest1:F src0:F -src1:F d875 2 a876 1 * (no changes) d884 1 a884 1 EXPECT_FALSE(cmod_propagation(v)); d886 1 a886 1 EXPECT_EQ(2, block0->end_ip); d888 1 a888 1 EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); d890 1 a890 3 EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 1)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 2)->conditional_mod); d893 1 a893 1 TEST_F(cmod_propagation_test, subtract_not_merge_with_compare_intervening_add) d896 7 a902 7 fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest0, src0, negate(src1)); set_condmod(BRW_CONDITIONAL_EQ, bld.ADD(dest1, src0, src1)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); d905 2 a906 3 * 0: add(8) dest0:F src0:F -src1:F * 1: add.z.f0(8) dest1:F src0:F src1:F * 2: cmp.l.f0(8) null:F src0:F src1:F d915 1 a915 1 EXPECT_EQ(2, block0->end_ip); d919 4 a922 2084 EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, add_merge_with_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest, src0, src1); bld.CMP(bld.null_reg_f(), src0, negate(src1), BRW_CONDITIONAL_L); /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: cmp.l.f0(8) null:F src0:F -src1:F * * = After = * 0: add.l.f0(8) dest:F src0:F src1:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, negative_subtract_merge_with_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest, src1, negate(src0)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* The result of the subtract is the negatiion of the result of the * implicit subtract in the compare, so the condition must change. * * = Before = * 0: add(8) dest:F src1:F -src0:F * 1: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.g.f0(8) dest:F src0:F -src1:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, subtract_delete_compare) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))); set_predicate(BRW_PREDICATE_NORMAL, bld.MOV(dest1, src2)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: (+f0) mov(0) dest1:F src2:F * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.l.f0(8) dest:F src0:F -src1:F * 1: (+f0) mov(0) dest1:F src2:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, subtract_delete_compare_other_flag) { /* This test is the same as subtract_delete_compare but it explicitly used * flag f0.1 for the subtraction and the comparison. */ const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))) ->flag_subreg = 1; set_predicate(BRW_PREDICATE_NORMAL, bld.MOV(dest1, src2)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L) ->flag_subreg = 1; /* = Before = * 0: add.l.f0.1(8) dest0:F src0:F -src1:F * 1: (+f0) mov(0) dest1:F src2:F * 2: cmp.l.f0.1(8) null:F src0:F src1:F * * = After = * 0: add.l.f0.1(8) dest:F src0:F -src1:F * 1: (+f0) mov(0) dest1:F src2:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(1, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, subtract_to_mismatch_flag) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest, src0, negate(src1))); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L) ->flag_subreg = 1; /* = Before = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: cmp.l.f0.1(8) null:F src0:F src1:F * * = After = * No changes */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_mismatch_flag_write) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest0, src0, negate(src1)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L) ->flag_subreg = 1; bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F * 1: cmp.l.f0.1(8) null:F src0:F src1:F * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: cmp.l.f0.1(8) null:F src0:F src1:F * * NOTE: Another perfectly valid after sequence would be: * * 0: add.f0.1(8) dest0:F src0:F -src1:F * 1: cmp.l.f0(8) null:F src0:F src1:F * * However, the optimization pass starts at the end of the basic block. * Because of this, the cmp.l.f0 will always be chosen. If the pass * changes its strategy, this test will also need to change. */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 1)->conditional_mod); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, subtract_merge_with_compare_intervening_mismatch_flag_read) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest0, src0, negate(src1)); set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) ->flag_subreg = 1; bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add(8) dest0:F src0:F -src1:F * 1: (+f0.1) sel(8) dest1 src2 0.0f * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: (+f0.1) sel(8) dest1 src2 0.0f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, subtract_delete_compare_derp) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::float_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); set_condmod(BRW_CONDITIONAL_L, bld.ADD(dest0, src0, negate(src1))); set_predicate(BRW_PREDICATE_NORMAL, bld.ADD(dest1, negate(src0), src1)); bld.CMP(bld.null_reg_f(), src0, src1, BRW_CONDITIONAL_L); /* = Before = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: (+f0) add(0) dest1:F -src0:F src1:F * 2: cmp.l.f0(8) null:F src0:F src1:F * * = After = * 0: add.l.f0(8) dest0:F src0:F -src1:F * 1: (+f0) add(0) dest1:F -src0:F src1:F */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_L, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, signed_unsigned_comparison_mismatch) { const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::int_type); fs_reg src0 = v->vgrf(glsl_type::int_type); src0.type = BRW_REGISTER_TYPE_W; bld.ASR(dest0, negate(src0), brw_imm_d(15)); bld.CMP(bld.null_reg_ud(), retype(dest0, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u), BRW_CONDITIONAL_LE); /* = Before = * 0: asr(8) dest:D -src0:W 15D * 1: cmp.le.f0(8) null:UD dest:UD 0UD * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ASR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, ior_f2i_nz) { const fs_builder &bld = v->bld; fs_reg dest = bld.vgrf(BRW_REGISTER_TYPE_D); fs_reg src0 = bld.vgrf(BRW_REGISTER_TYPE_D); fs_reg src1 = bld.vgrf(BRW_REGISTER_TYPE_D); bld.OR(dest, src0, src1); bld.MOV(bld.null_reg_d(), retype(dest, BRW_REGISTER_TYPE_F)) ->conditional_mod = BRW_CONDITIONAL_NZ; /* = Before = * 0: or(8) dest:D src0:D src1:D * 1: mov.nz(8) null:D dest:F * * = After = * No changes. * * If src0 = 0x30000000 and src1 = 0x0f000000, then the value stored in * dest, interpreted as floating point, is 0.5. This bit pattern is not * zero, but after the float-to-integer conversion, the value is zero. */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); /* This is ASSERT_EQ because if end_ip is 0, the instruction(block0, 1) * calls will not work properly, and the test will give weird results. */ ASSERT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } void cmod_propagation_test::test_mov_prop(enum brw_conditional_mod cmod, enum brw_reg_type add_type, enum brw_reg_type mov_dst_type, bool expected_cmod_prop_progress) { const fs_builder &bld = v->bld; fs_reg dest = bld.vgrf(add_type); fs_reg src0 = bld.vgrf(add_type); fs_reg src1 = bld.vgrf(add_type); bld.ADD(dest, src0, src1); bld.MOV(retype(bld.null_reg_ud(), mov_dst_type), dest) ->conditional_mod = cmod; v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(expected_cmod_prop_progress, cmod_propagation(v)); const enum brw_conditional_mod add_cmod = expected_cmod_prop_progress ? cmod : BRW_CONDITIONAL_NONE; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(add_cmod, instruction(block0, 0)->conditional_mod); if (expected_cmod_prop_progress) { EXPECT_EQ(0, block0->end_ip); } else { /* This is ASSERT_EQ because if end_ip is 0, the instruction(block0, 1) * calls will not work properly, and the test will give weird results. */ ASSERT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode); EXPECT_EQ(cmod, instruction(block0, 1)->conditional_mod); } } TEST_F(cmod_propagation_test, fadd_fmov_nz) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.nz(8) null:F dest:F * * = After = * 0: add.nz(8) dest:F src0:F src1:F */ test_mov_prop(BRW_CONDITIONAL_NZ, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, fadd_fmov_z) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.z(8) null:F dest:F * * = After = * 0: add.z(8) dest:F src0:F src1:F */ test_mov_prop(BRW_CONDITIONAL_Z, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, fadd_fmov_l) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.l(8) null:F dest:F * * = After = * 0: add.l(8) dest:F src0:F src1:F */ test_mov_prop(BRW_CONDITIONAL_L, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, fadd_fmov_g) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.g(8) null:F dest:F * * = After = * 0: add.g(8) dest:F src0:F src1:F */ test_mov_prop(BRW_CONDITIONAL_G, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, fadd_fmov_le) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.le(8) null:F dest:F * * = After = * 0: add.le(8) dest:F src0:F src1:F */ test_mov_prop(BRW_CONDITIONAL_LE, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, fadd_fmov_ge) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.ge(8) null:F dest:F * * = After = * 0: add.ge(8) dest:F src0:F src1:F */ test_mov_prop(BRW_CONDITIONAL_GE, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, iadd_imov_nz) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.nz(8) null:D dest:D * * = After = * 0: add.nz(8) dest:D src0:D src1:D */ test_mov_prop(BRW_CONDITIONAL_NZ, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, iadd_imov_z) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.z(8) null:D dest:D * * = After = * 0: add.z(8) dest:D src0:D src1:D */ test_mov_prop(BRW_CONDITIONAL_Z, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, iadd_imov_l) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.l(8) null:D dest:D * * = After = * 0: add.l(8) dest:D src0:D src1:D */ test_mov_prop(BRW_CONDITIONAL_L, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, iadd_imov_g) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.g(8) null:D dest:D * * = After = * 0: add.g(8) dest:D src0:D src1:D */ test_mov_prop(BRW_CONDITIONAL_G, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, iadd_imov_le) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.le(8) null:D dest:D * * = After = * 0: add.le(8) dest:D src0:D src1:D */ test_mov_prop(BRW_CONDITIONAL_LE, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, iadd_imov_ge) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.ge(8) null:D dest:D * * = After = * 0: add.ge(8) dest:D src0:D src1:D */ test_mov_prop(BRW_CONDITIONAL_GE, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, iadd_umov_nz) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.nz(8) null:UD dest:D * * = After = * 0: add.nz(8) dest:D src0:D src1:D */ test_mov_prop(BRW_CONDITIONAL_NZ, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_UD, true); } TEST_F(cmod_propagation_test, iadd_umov_z) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.z(8) null:UD dest:D * * = After = * 0: add.z(8) dest:D src0:D src1:D */ test_mov_prop(BRW_CONDITIONAL_Z, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_UD, true); } TEST_F(cmod_propagation_test, iadd_umov_l) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.l(8) null:UD dest:D * * = After = * No changes. * * Due to the signed-to-usigned type conversion, the conditional modifier * cannot be propagated to the ADD without changing at least the * destination type of the add. * * This particular tests is a little silly. Unsigned less than zero is a * contradiction, and earlier optimization passes should have eliminated * it. */ test_mov_prop(BRW_CONDITIONAL_L, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, iadd_umov_g) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.g(8) null:UD dest:D * * = After = * No changes. * * In spite of the type conversion, this could be made to work by * propagating NZ instead of G to the ADD. */ test_mov_prop(BRW_CONDITIONAL_G, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, iadd_umov_le) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.le(8) null:UD dest:D * * = After = * No changes. * * In spite of the type conversion, this could be made to work by * propagating Z instead of LE to the ADD. */ test_mov_prop(BRW_CONDITIONAL_LE, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, iadd_umov_ge) { /* = Before = * 0: add(8) dest:D src0:D src1:D * 1: mov.ge(8) null:UD dest:D * * = After = * No changes. * * Due to the signed-to-usigned type conversion, the conditional modifier * cannot be propagated to the ADD without changing at least the * destination type of the add. * * This particular tests is a little silly. Unsigned greater than or equal * to zero is a tautology, and earlier optimization passes should have * eliminated it. */ test_mov_prop(BRW_CONDITIONAL_GE, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, fadd_f2u_nz) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.nz(8) null:UD dest:F * * = After = * No changes. The MOV changes the type from float to unsigned integer. * If dest is in the range [-Inf, 1), the conversion will clamp it to zero. * If dest is NaN, the conversion will also clamp it to zero. It is not * safe to propagate the NZ back to the ADD. * * It's tempting to try to propagate G to the ADD in place of the NZ. This * fails for values (0, 1). For example, if dest is 0.5, add.g would set * the flag, but mov.nz would not because the 0.5 would get rounded down to * zero. */ test_mov_prop(BRW_CONDITIONAL_NZ, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, fadd_f2u_z) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.z(8) null:UD dest:F * * = After = * No changes. * * The MOV changes the type from float to unsigned integer. If dest is in * the range [-Inf, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the Z back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_Z, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, fadd_f2u_l) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.l(8) null:UD dest:F * * = After = * No changes. * * The MOV changes the type from float to unsigned integer. If dest is in * the range [-Inf, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the L back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_L, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, fadd_f2u_g) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.g(8) null:UD dest:F * * = After = * No changes. * * The MOV changes the type from float to unsigned integer. If dest is in * the range [-Inf, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the G back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_G, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, fadd_f2u_le) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.le(8) null:UD dest:F * * = After = * No changes. * * The MOV changes the type from float to unsigned integer. If dest is in * the range [-Inf, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the LE back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_LE, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, fadd_f2u_ge) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.ge(8) null:UD dest:F * * = After = * No changes. * * The MOV changes the type from float to unsigned integer. If dest is in * the range [-Inf, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the GE back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_GE, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_UD, false); } TEST_F(cmod_propagation_test, fadd_f2i_nz) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.nz(8) null:D dest:F * * = After = * No changes. The MOV changes the type from float to signed integer. If * dest is in the range (-1, 1), the conversion will clamp it to zero. If * dest is NaN, the conversion will also clamp it to zero. It is not safe * to propagate the NZ back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_NZ, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_D, false); } TEST_F(cmod_propagation_test, fadd_f2i_z) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.z(8) null:D dest:F * * = After = * No changes. * * The MOV changes the type from float to signed integer. If dest is in * the range (-1, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the Z back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_Z, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_D, false); } TEST_F(cmod_propagation_test, fadd_f2i_l) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.l(8) null:D dest:F * * = After = * No changes. * * The MOV changes the type from float to signed integer. If dest is in * the range (-1, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the L back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_L, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_D, false); } TEST_F(cmod_propagation_test, fadd_f2i_g) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.g(8) null:D dest:F * * = After = * No changes. * * The MOV changes the type from float to signed integer. If dest is in * the range (-1, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the G back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_G, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_D, false); } TEST_F(cmod_propagation_test, fadd_f2i_le) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.le(8) null:D dest:F * * = After = * No changes. * * The MOV changes the type from float to signed integer. If dest is in * the range (-1, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the LE back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_LE, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_D, false); } TEST_F(cmod_propagation_test, fadd_f2i_ge) { /* = Before = * 0: add(8) dest:F src0:F src1:F * 1: mov.ge(8) null:D dest:F * * = After = * No changes. * * The MOV changes the type from float to signed integer. If dest is in * the range (-1, 1), the conversion will clamp it to zero. If dest is * NaN, the conversion will also clamp it to zero. It is not safe to * propagate the GE back to the ADD. */ test_mov_prop(BRW_CONDITIONAL_GE, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_D, false); } void cmod_propagation_test::test_saturate_prop(enum brw_conditional_mod before, enum opcode op, enum brw_reg_type add_type, enum brw_reg_type op_type, bool expected_cmod_prop_progress) { const fs_builder &bld = v->bld; fs_reg dest = bld.vgrf(add_type); fs_reg src0 = bld.vgrf(add_type); fs_reg src1 = bld.vgrf(add_type); fs_reg zero(brw_imm_ud(0)); bld.ADD(dest, src0, src1)->saturate = true; assert(op == BRW_OPCODE_CMP || op == BRW_OPCODE_MOV); if (op == BRW_OPCODE_CMP) { bld.CMP(bld.vgrf(op_type, 0), retype(dest, op_type), retype(zero, op_type), before); } else { bld.MOV(bld.vgrf(op_type, 0), retype(dest, op_type)) ->conditional_mod = before; } v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(expected_cmod_prop_progress, cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(add_type, instruction(block0, 0)->dst.type); EXPECT_EQ(add_type, instruction(block0, 0)->src[0].type); EXPECT_EQ(add_type, instruction(block0, 0)->src[1].type); EXPECT_TRUE(instruction(block0, 0)->saturate); if (expected_cmod_prop_progress) { EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(before, instruction(block0, 0)->conditional_mod); } else { EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); /* This is ASSERT_EQ because if end_ip is 0, the instruction(block0, 1) * calls will not work properly, and the test will give weird results. */ ASSERT_EQ(1, block0->end_ip); EXPECT_EQ(op, instruction(block0, 1)->opcode); EXPECT_EQ(op_type, instruction(block0, 1)->dst.type); EXPECT_EQ(op_type, instruction(block0, 1)->src[0].type); EXPECT_FALSE(instruction(block0, 1)->saturate); EXPECT_EQ(before, instruction(block0, 1)->conditional_mod); } } TEST_F(cmod_propagation_test, float_saturate_nz_cmp) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.nz.f0(8) null dest 0.0f * * = After = * 0: add.sat.nz.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_nz_mov) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.nz.f0(8) null dest * * = After = * 0: add.sat.nz.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_z_cmp) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.z.f0(8) null dest 0.0f * * = After = * 0: add.sat.z.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_z_mov) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.z.f0(8) null dest * * = After = * 0: add.sat.z.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_g_cmp) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.g.f0(8) null dest 0.0f * * = After = * 0: add.sat.g.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_G, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_g_mov) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.g.f0(8) null dest * * = After = * 0: add.sat.g.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_G, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_le_cmp) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.le.f0(8) null dest 0.0f * * = After = * 0: add.sat.le.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_LE, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_le_mov) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. (sat(x) <= 0) == (x <= 0). * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.le.f0(8) null dest * * = After = * 0: add.sat.le.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_LE, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_l_cmp) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.l.f0(8) null dest 0.0f * * = After = * 0: add.sat.l.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_L, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_l_mov) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.l.f0(8) null dest * * = After = * 0: add.sat.l.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_L, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_ge_cmp) { /* With the saturate modifier, the comparison happens after clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.ge.f0(8) null dest 0.0f * * = After = * 0: add.sat.ge.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_GE, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, float_saturate_ge_mov) { /* With the saturate modifier, the comparison happens before clamping to * [0, 1]. * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.ge.f0(8) null dest * * = After = * 0: add.sat.ge.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_GE, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_F, BRW_REGISTER_TYPE_F, true); } TEST_F(cmod_propagation_test, int_saturate_nz_cmp) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.nz.f0(8) null dest 0 * * = After = * 0: add.sat.nz.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, uint_saturate_nz_cmp) { /* = Before = * * 0: add.sat(8) dest:UD src0:UD src1:UD * 1: cmp.nz.f0(8) null:D dest:D 0 * * = After = * 0: add.sat.nz.f0(8) dest:UD src0:UD src1:UD */ test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_UD, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_nz_mov) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.nz.f0(8) null dest * * = After = * 0: add.sat.nz.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_NZ, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_z_cmp) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.z.f0(8) null dest 0 * * = After = * 0: add.sat.z.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, uint_saturate_z_cmp) { /* = Before = * * 0: add.sat(8) dest:UD src0:UD src1:UD * 1: cmp.z.f0(8) null:D dest:D 0 * * = After = * 0: add.sat.z.f0(8) dest:UD src0:UD src1:UD */ test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_UD, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_z_mov) { /* With the saturate modifier, the comparison happens before clamping to * [0, 1]. (sat(x) == 0) == (x <= 0). * * = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.z.f0(8) null dest * * = After = * 0: add.sat.z.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_Z, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_g_cmp) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.g.f0(8) null dest 0 * * = After = * 0: add.sat.g.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_G, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_g_mov) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.g.f0(8) null dest * * = After = * 0: add.sat.g.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_G, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_le_cmp) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.le.f0(8) null dest 0 * * = After = * 0: add.sat.le.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_LE, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_le_mov) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.le.f0(8) null dest * * = After = * 0: add.sat.le.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_LE, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_l_cmp) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.l.f0(8) null dest 0 * * = After = * 0: add.sat.l.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_L, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_l_mov) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.l.f0(8) null dest 0 * * = After = * 0: add.sat.l.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_L, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_ge_cmp) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: cmp.ge.f0(8) null dest 0 * * = After = * 0: add.sat.ge.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_GE, BRW_OPCODE_CMP, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, int_saturate_ge_mov) { /* = Before = * * 0: add.sat(8) dest src0 src1 * 1: mov.ge.f0(8) null dest * * = After = * 0: add.sat.ge.f0(8) dest src0 src1 */ test_saturate_prop(BRW_CONDITIONAL_GE, BRW_OPCODE_MOV, BRW_REGISTER_TYPE_D, BRW_REGISTER_TYPE_D, true); } TEST_F(cmod_propagation_test, not_to_or) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::uint_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg src1 = v->vgrf(glsl_type::uint_type); bld.OR(dest, src0, src1); set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); /* = Before = * * 0: or(8) dest src0 src1 * 1: not.nz.f0(8) null dest * * = After = * 0: or.z.f0(8) dest src0 src1 */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_and) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::uint_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg src1 = v->vgrf(glsl_type::uint_type); bld.AND(dest, src0, src1); set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); /* = Before = * * 0: and(8) dest src0 src1 * 1: not.nz.f0(8) null dest * * = After = * 0: and.z.f0(8) dest src0 src1 */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_AND, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_uadd) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. * * The optimization pass currently restricts to just OR and AND. It's * possible that this is too restrictive, and the actual, necessary * restriction is just the the destination type of the ALU instruction is * the same as the source type of the NOT instruction. */ const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::uint_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg src1 = v->vgrf(glsl_type::uint_type); bld.ADD(dest, src0, src1); set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); /* = Before = * * 0: add(8) dest src0 src1 * 1: not.nz.f0(8) null dest * * = After = * No changes */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_fadd_to_ud) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. * * The optimization pass currently restricts to just OR and AND. It's * possible that this is too restrictive, and the actual, necessary * restriction is just the the destination type of the ALU instruction is * the same as the source type of the NOT instruction. */ const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::uint_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest, src0, src1); set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest)); /* = Before = * * 0: add(8) dest.ud src0.f src1.f * 1: not.nz.f0(8) null dest.ud * * = After = * No changes */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_fadd) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. * * The optimization pass currently restricts to just OR and AND. It's * possible that this is too restrictive, and the actual, necessary * restriction is just the the destination type of the ALU instruction is * the same as the source type of the NOT instruction. */ const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); bld.ADD(dest, src0, src1); set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), retype(dest, BRW_REGISTER_TYPE_UD))); /* = Before = * * 0: add(8) dest.f src0.f src1.f * 1: not.nz.f0(8) null dest.ud * * = After = * No changes */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_compatible_value) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::uint_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg src1 = v->vgrf(glsl_type::uint_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest0, src0, src1)); set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * * 0: or.z.f0(8) dest0 src0 src1 * 1: (+f0) sel(8) dest1 src2 0.0f * 2: not.nz.f0(8) null dest0 * * = After = * 0: or.z.f0(8) dest0 src0 src1 * 1: (+f0) sel(8) dest1 src2 0.0f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); } TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_compatible_value_mismatch_flag) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::uint_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg src1 = v->vgrf(glsl_type::uint_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest0, src0, src1)) ->flag_subreg = 1; set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * * 0: or.z.f0.1(8) dest0 src0 src1 * 1: (+f0) sel(8) dest1 src2 0.0f * 2: not.nz.f0(8) null dest0 * * = After = * No changes */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); EXPECT_EQ(1, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 2)->conditional_mod); EXPECT_EQ(0, instruction(block0, 2)->flag_subreg); } TEST_F(cmod_propagation_test, not_to_or_intervening_flag_read_incompatible_value) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::uint_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg src1 = v->vgrf(glsl_type::uint_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); set_condmod(BRW_CONDITIONAL_NZ, bld.OR(dest0, src0, src1)); set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)); set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * * 0: or.nz.f0(8) dest0 src0 src1 * 1: (+f0) sel(8) dest1 src2 0.0f * 2: not.nz.f0(8) null dest0 * * = After = * No changes */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(BRW_OPCODE_NOT, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NZ, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_write) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::uint_type); fs_reg dest1 = v->vgrf(glsl_type::uint_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg src1 = v->vgrf(glsl_type::uint_type); bld.OR(dest0, src0, src1); set_condmod(BRW_CONDITIONAL_Z, bld.OR(dest1, src0, src1)) ->flag_subreg = 1; set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * * 0: or(8) dest0 src0 src1 * 1: or.z.f0.1(8) dest1 src0 src1 * 2: not.nz.f0(8) null dest0 * * = After = * 0: or.z.f0(8) dest0 src0 src1 * 1: or.z.f0.1(8) dest1 src0 src1 */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 1)->conditional_mod); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, not_to_or_intervening_mismatch_flag_read) { /* Exercise propagation of conditional modifier from a NOT instruction to * another ALU instruction as performed by cmod_propagate_not. */ const fs_builder &bld = v->bld; fs_reg dest0 = v->vgrf(glsl_type::uint_type); fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::uint_type); fs_reg src1 = v->vgrf(glsl_type::uint_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.OR(dest0, src0, src1); set_predicate(BRW_PREDICATE_NORMAL, bld.SEL(dest1, src2, zero)) ->flag_subreg = 1; set_condmod(BRW_CONDITIONAL_NZ, bld.NOT(bld.null_reg_ud(), dest0)); /* = Before = * * 0: or(8) dest0 src0 src1 * 1: (+f0.1) sel(8) dest1 src2 0.0f * 2: not.nz.f0(8) null dest0 * * = After = * 0: or.z.f0(8) dest0 src0 src1 * 1: (+f0.1) sel(8) dest1 src2 0.0f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_OR, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_Z, instruction(block0, 0)->conditional_mod); EXPECT_EQ(0, instruction(block0, 0)->flag_subreg); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_PREDICATE_NORMAL, instruction(block0, 1)->predicate); EXPECT_EQ(1, instruction(block0, 1)->flag_subreg); } TEST_F(cmod_propagation_test, cmp_to_add_float_e) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg neg10(brw_imm_f(-10.0f)); fs_reg pos10(brw_imm_f(10.0f)); bld.ADD(dest, src0, neg10)->saturate = true; bld.CMP(bld.null_reg_f(), src0, pos10, BRW_CONDITIONAL_EQ); /* = Before = * 0: add.sat(8) vgrf0:F, vgrf1:F, -10f * 1: cmp.z.f0.0(8) null:F, vgrf1:F, 10f * * = After = * (no changes) */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_EQ, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_to_add_float_g) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg neg10(brw_imm_f(-10.0f)); fs_reg pos10(brw_imm_f(10.0f)); bld.ADD(dest, src0, neg10)->saturate = true; bld.CMP(bld.null_reg_f(), src0, pos10, BRW_CONDITIONAL_G); /* = Before = * 0: add.sat(8) vgrf0:F, vgrf1:F, -10f * 1: cmp.g.f0.0(8) null:F, vgrf1:F, 10f * * = After = * 0: add.sat.g.f0.0(8) vgrf0:F, vgrf1:F, -10f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_G, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, cmp_to_add_float_le) { const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg neg10(brw_imm_f(-10.0f)); fs_reg pos10(brw_imm_f(10.0f)); bld.ADD(dest, src0, neg10)->saturate = true; bld.CMP(bld.null_reg_f(), src0, pos10, BRW_CONDITIONAL_LE); /* = Before = * 0: add.sat(8) vgrf0:F, vgrf1:F, -10f * 1: cmp.le.f0.0(8) null:F, vgrf1:F, 10f * * = After = * 0: add.sat.le.f0.0(8) vgrf0:F, vgrf1:F, -10f */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(0, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_LE, instruction(block0, 0)->conditional_mod); } TEST_F(cmod_propagation_test, prop_across_sel_gfx7) { const fs_builder &bld = v->bld; fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg dest2 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg src3 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest1, src0, src1); bld.emit_minmax(dest2, src2, src3, BRW_CONDITIONAL_GE); bld.CMP(bld.null_reg_f(), dest1, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest1 src0 src1 * 1: sel.ge(8) dest2 src2 src3 * 2: cmp.ge.f0(8) null dest1 0.0f * * = After = * 0: add.ge.f0(8) dest1 src0 src1 * 1: sel.ge(8) dest2 src2 src3 */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_TRUE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); } TEST_F(cmod_propagation_test, prop_across_sel_gfx5) { devinfo->ver = 5; devinfo->verx10 = devinfo->ver * 10; const fs_builder &bld = v->bld; fs_reg dest1 = v->vgrf(glsl_type::float_type); fs_reg dest2 = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg src2 = v->vgrf(glsl_type::float_type); fs_reg src3 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.ADD(dest1, src0, src1); bld.emit_minmax(dest2, src2, src3, BRW_CONDITIONAL_GE); bld.CMP(bld.null_reg_f(), dest1, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: add(8) dest1 src0 src1 * 1: sel.ge(8) dest2 src2 src3 * 2: cmp.ge.f0(8) null dest1 0.0f * * = After = * (no changes) * * On Gfx4 and Gfx5, sel.l (for min) and sel.ge (for max) are implemented * using a separate cmpn and sel instruction. This lowering occurs in * fs_vistor::lower_minmax which is called a long time after the first * calls to cmod_propagation. */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(2, block0->end_ip); EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_NONE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 2)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 2)->conditional_mod); } TEST_F(cmod_propagation_test, prop_into_sel_gfx5) { devinfo->ver = 5; devinfo->verx10 = devinfo->ver * 10; const fs_builder &bld = v->bld; fs_reg dest = v->vgrf(glsl_type::float_type); fs_reg src0 = v->vgrf(glsl_type::float_type); fs_reg src1 = v->vgrf(glsl_type::float_type); fs_reg zero(brw_imm_f(0.0f)); bld.emit_minmax(dest, src0, src1, BRW_CONDITIONAL_GE); bld.CMP(bld.null_reg_f(), dest, zero, BRW_CONDITIONAL_GE); /* = Before = * * 0: sel.ge(8) dest src0 src1 * 1: cmp.ge.f0(8) null dest 0.0f * * = After = * (no changes) * * Do not copy propagate into a sel.cond instruction. While it does modify * the flags, the flags are not based on the result compared with zero (as * with most other instructions). The result is based on the sources * compared with each other (like cmp.cond). */ v->calculate_cfg(); bblock_t *block0 = v->cfg->blocks[0]; EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_FALSE(cmod_propagation(v)); EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); EXPECT_EQ(BRW_OPCODE_SEL, instruction(block0, 0)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 0)->conditional_mod); EXPECT_EQ(BRW_OPCODE_CMP, instruction(block0, 1)->opcode); EXPECT_EQ(BRW_CONDITIONAL_GE, instruction(block0, 1)->conditional_mod); @