head	1.1;
branch	1.1.1;
access;
symbols
	netbsd-11-0-RC4:1.1.1.3
	netbsd-11-0-RC3:1.1.1.3
	netbsd-11-0-RC2:1.1.1.3
	netbsd-11-0-RC1:1.1.1.3
	netbsd-11:1.1.1.3.0.4
	netbsd-11-base:1.1.1.3
	netbsd-10-1-RELEASE:1.1.1.3
	netbsd-9-4-RELEASE:1.1.1.1
	netbsd-10-0-RELEASE:1.1.1.3
	netbsd-10-0-RC6:1.1.1.3
	netbsd-10-0-RC5:1.1.1.3
	netbsd-10-0-RC4:1.1.1.3
	netbsd-10-0-RC3:1.1.1.3
	netbsd-10-0-RC2:1.1.1.3
	netbsd-10-0-RC1:1.1.1.3
	netbsd-10:1.1.1.3.0.2
	netbsd-10-base:1.1.1.3
	netbsd-9-3-RELEASE:1.1.1.1
	mesa-21-3-7:1.1.1.3
	netbsd-9-2-RELEASE:1.1.1.1
	netbsd-9-1-RELEASE:1.1.1.1
	netbsd-9-0-RELEASE:1.1.1.1
	netbsd-9-0-RC2:1.1.1.1
	netbsd-9-0-RC1:1.1.1.1
	mesalib-19-1-7:1.1.1.2
	netbsd-9:1.1.1.1.0.2
	netbsd-9-base:1.1.1.1
	mesa-18-3-6:1.1.1.1
	mesa-18-3-4:1.1.1.1
	xorg:1.1.1;
locks; strict;
comment	@// @;


1.1
date	2019.03.10.03.42.41;	author mrg;	state Exp;
branches
	1.1.1.1;
next	;
commitid	r12jo1Nf3ebQKLeB;

1.1.1.1
date	2019.03.10.03.42.41;	author mrg;	state Exp;
branches;
next	1.1.1.2;
commitid	r12jo1Nf3ebQKLeB;

1.1.1.2
date	2019.09.24.17.41.26;	author maya;	state Exp;
branches;
next	1.1.1.3;
commitid	KJXusGl8fi9AAhEB;

1.1.1.3
date	2022.05.09.01.23.37;	author mrg;	state Exp;
branches;
next	;
commitid	UEBs6hNk81DdQjDD;


desc
@@


1.1
log
@Initial revision
@
text
@/*
 * Copyright © 2012 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#include <gtest/gtest.h>
#include "brw_vec4.h"
#include "program/program.h"

using namespace brw;

int ret = 0;

#define register_coalesce(v) _register_coalesce(v, __func__)

class register_coalesce_test : public ::testing::Test {
   virtual void SetUp();

public:
   struct brw_compiler *compiler;
   struct gen_device_info *devinfo;
   struct gl_context *ctx;
   struct gl_shader_program *shader_prog;
   struct brw_vue_prog_data *prog_data;
   vec4_visitor *v;
};


class register_coalesce_vec4_visitor : public vec4_visitor
{
public:
   register_coalesce_vec4_visitor(struct brw_compiler *compiler,
                                  nir_shader *shader,
                                  struct brw_vue_prog_data *prog_data)
      : vec4_visitor(compiler, NULL, NULL, prog_data, shader, NULL,
                     false /* no_spills */, -1)
   {
      prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
   }

protected:
   virtual dst_reg *make_reg_for_system_value(int location)
   {
      unreachable("Not reached");
   }

   virtual void setup_payload()
   {
      unreachable("Not reached");
   }

   virtual void emit_prolog()
   {
      unreachable("Not reached");
   }

   virtual void emit_thread_end()
   {
      unreachable("Not reached");
   }

   virtual void emit_urb_write_header(int mrf)
   {
      unreachable("Not reached");
   }

   virtual vec4_instruction *emit_urb_write_opcode(bool complete)
   {
      unreachable("Not reached");
   }
};


void register_coalesce_test::SetUp()
{
   ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
   compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
   devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
   prog_data = (struct brw_vue_prog_data *)calloc(1, sizeof(*prog_data));
   compiler->devinfo = devinfo;

   nir_shader *shader =
      nir_shader_create(NULL, MESA_SHADER_VERTEX, NULL, NULL);

   v = new register_coalesce_vec4_visitor(compiler, shader, prog_data);

   devinfo->gen = 4;
}

static void
_register_coalesce(vec4_visitor *v, const char *func)
{
   bool print = false;

   if (print) {
      printf("%s: instructions before:\n", func);
      v->dump_instructions();
   }

   v->calculate_cfg();
   v->opt_register_coalesce();

   if (print) {
      printf("%s: instructions after:\n", func);
      v->dump_instructions();
   }
}

TEST_F(register_coalesce_test, test_compute_to_mrf)
{
   src_reg something = src_reg(v, glsl_type::float_type);
   dst_reg temp = dst_reg(v, glsl_type::float_type);
   dst_reg init;

   dst_reg m0 = dst_reg(MRF, 0);
   m0.writemask = WRITEMASK_X;
   m0.type = BRW_REGISTER_TYPE_F;

   vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
   v->emit(v->MOV(m0, src_reg(temp)));

   register_coalesce(v);

   EXPECT_EQ(mul->dst.file, MRF);
}


TEST_F(register_coalesce_test, test_multiple_use)
{
   src_reg something = src_reg(v, glsl_type::float_type);
   dst_reg temp = dst_reg(v, glsl_type::vec4_type);
   dst_reg init;

   dst_reg m0 = dst_reg(MRF, 0);
   m0.writemask = WRITEMASK_X;
   m0.type = BRW_REGISTER_TYPE_F;

   dst_reg m1 = dst_reg(MRF, 1);
   m1.writemask = WRITEMASK_XYZW;
   m1.type = BRW_REGISTER_TYPE_F;

   src_reg src = src_reg(temp);
   vec4_instruction *mul = v->emit(v->MUL(temp, something, brw_imm_f(1.0f)));
   src.swizzle = BRW_SWIZZLE_XXXX;
   v->emit(v->MOV(m0, src));
   src.swizzle = BRW_SWIZZLE_XYZW;
   v->emit(v->MOV(m1, src));

   register_coalesce(v);

   EXPECT_NE(mul->dst.file, MRF);
}

TEST_F(register_coalesce_test, test_dp4_mrf)
{
   src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
   src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
   dst_reg init;

   dst_reg m0 = dst_reg(MRF, 0);
   m0.writemask = WRITEMASK_Y;
   m0.type = BRW_REGISTER_TYPE_F;

   dst_reg temp = dst_reg(v, glsl_type::float_type);

   vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
   v->emit(v->MOV(m0, src_reg(temp)));

   register_coalesce(v);

   EXPECT_EQ(dp4->dst.file, MRF);
   EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
}

TEST_F(register_coalesce_test, test_dp4_grf)
{
   src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
   src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
   dst_reg init;

   dst_reg to = dst_reg(v, glsl_type::vec4_type);
   dst_reg temp = dst_reg(v, glsl_type::float_type);

   vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2));
   to.writemask = WRITEMASK_Y;
   v->emit(v->MOV(to, src_reg(temp)));

   /* if we don't do something with the result, the automatic dead code
    * elimination will remove all our instructions.
    */
   src_reg src = src_reg(to);
   src.negate = true;
   v->emit(v->MOV(dst_reg(MRF, 0), src));

   register_coalesce(v);

   EXPECT_EQ(dp4->dst.nr, to.nr);
   EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y);
}

TEST_F(register_coalesce_test, test_channel_mul_grf)
{
   src_reg some_src_1 = src_reg(v, glsl_type::vec4_type);
   src_reg some_src_2 = src_reg(v, glsl_type::vec4_type);
   dst_reg init;

   dst_reg to = dst_reg(v, glsl_type::vec4_type);
   dst_reg temp = dst_reg(v, glsl_type::float_type);

   vec4_instruction *mul = v->emit(v->MUL(temp, some_src_1, some_src_2));
   to.writemask = WRITEMASK_Y;
   v->emit(v->MOV(to, src_reg(temp)));

   /* if we don't do something with the result, the automatic dead code
    * elimination will remove all our instructions.
    */
   src_reg src = src_reg(to);
   src.negate = true;
   v->emit(v->MOV(dst_reg(MRF, 0), src));

   register_coalesce(v);

   EXPECT_EQ(mul->dst.nr, to.nr);
}
@


1.1.1.1
log
@from maya:

Import mesa 18.3.4.

Mesa 18.3.4 implements the OpenGL 4.5 API.
Some drivers don't support all the features required in OpenGL 4.5.
@
text
@@


1.1.1.2
log
@Import mesa 19.1.7

New features in mesa 19.1.0:

    GL_ARB_parallel_shader_compile on all drivers.
    GL_EXT_gpu_shader4 on all GL 3.1 drivers.
    GL_EXT_shader_image_load_formatted on radeonsi.
    GL_EXT_texture_buffer_object on all GL 3.1 drivers.
    GL_EXT_texture_compression_s3tc_srgb on Gallium drivers and i965 (ES extension).
    GL_NV_compute_shader_derivatives on iris and i965.
    GL_KHR_parallel_shader_compile on all drivers.
    VK_EXT_buffer_device_address on Intel and RADV.
    VK_EXT_depth_clip_enable on Intel and RADV.
    VK_KHR_ycbcr_image_arrays on Intel.
    VK_EXT_inline_uniform_block on Intel and RADV.
    VK_EXT_external_memory_host on Intel.
    VK_EXT_host_query_reset on Intel and RADV.
    VK_KHR_surface_protected_capabilities on Intel and RADV.
    VK_EXT_pipeline_creation_feedback on Intel and RADV.
    VK_KHR_8bit_storage on RADV.
    VK_AMD_gpu_shader_int16 on RADV.
    VK_AMD_gpu_shader_half_float on RADV.
    VK_NV_compute_shader_derivatives on Intel.
    VK_KHR_shader_float16_int8 on Intel and RADV (RADV only supports int8).
    VK_KHR_shader_atomic_int64 on Intel.
    VK_EXT_descriptor_indexing on Intel.
    VK_KHR_shader_float16_int8 on Intel and RADV.
    GL_INTEL_conservative_rasterization on iris.
    VK_EXT_memory_budget on Intel.

New features in mesa 19.0.0:

    GL_AMD_texture_texture4 on all GL 4.0 drivers.
    GL_EXT_shader_implicit_conversions on all drivers (ES extension).
    GL_EXT_texture_compression_bptc on all GL 4.0 drivers (ES extension).
    GL_EXT_texture_compression_rgtc on all GL 3.0 drivers (ES extension).
    GL_EXT_render_snorm on gallium drivers (ES extension).
    GL_EXT_texture_view on drivers supporting texture views (ES extension).
    GL_OES_texture_view on drivers supporting texture views (ES extension).
    GL_NV_shader_atomic_float on nvc0 (Fermi/Kepler only).
    Shader-based software implementations of GL_ARB_gpu_shader_fp64, GL_ARB_gpu_shader_int64, GL_ARB_vertex_attrib_64bit, and GL_ARB_shader_ballot on i965.
    VK_ANDROID_external_memory_android_hardware_buffer on Intel
    Fixed and re-exposed VK_EXT_pci_bus_info on Intel and RADV
    VK_EXT_scalar_block_layout on Intel and RADV
    VK_KHR_depth_stencil_resolve on Intel
    VK_KHR_draw_indirect_count on Intel
    VK_EXT_conditional_rendering on Intel
    VK_EXT_memory_budget on RADV

Also, bug fixes.
@
text
@d60 1
a60 1
   virtual dst_reg *make_reg_for_system_value(int /* location */)
d80 1
a80 1
   virtual void emit_urb_write_header(int /* mrf */)
d85 1
a85 1
   virtual vec4_instruction *emit_urb_write_opcode(bool /* complete */)
@


1.1.1.3
log
@initial import of mesa 21.3.7

main changes since 19.1.7 include:
- more support for Vulkan functions
- better supported for newer radeonsi (both amdgpu and radeon backends)
- various bug fixes in many drivers
- many fixes and enhancements for intel drivers
- some fixes for nvidia
- OpenGL 4.6 for some drivers (intel, radeonsi)
- intel Tigerlake and Rocketlake support
- Vulkan 1.2 for some drivers
- OpenGL 4.5, GLES 3.2, and more on llvmpipe
- working Panfrost and Midgard drivers
- fix warnings in radeonsi vs newer llvm
@
text
@d30 2
a35 1
   virtual void TearDown();
d39 2
a40 2
   struct intel_device_info *devinfo;
   void *ctx;
a50 1
                                  void *mem_ctx,
d53 2
a54 2
      : vec4_visitor(compiler, NULL, NULL, prog_data, shader, mem_ctx,
                     false /* no_spills */, -1, false)
d94 4
a97 3
   ctx = ralloc_context(NULL);
   compiler = rzalloc(ctx, struct brw_compiler);
   devinfo = rzalloc(ctx, struct intel_device_info);
a99 2
   prog_data = ralloc(ctx, struct brw_vue_prog_data);

d101 1
a101 3
      nir_shader_create(ctx, MESA_SHADER_VERTEX, NULL, NULL);

   v = new register_coalesce_vec4_visitor(compiler, ctx, shader, prog_data);
d103 1
a103 8
   devinfo->ver = 4;
   devinfo->verx10 = devinfo->ver * 10;
}

void register_coalesce_test::TearDown()
{
   delete v;
   v = NULL;
d105 1
a105 2
   ralloc_free(ctx);
   ctx = NULL;
d111 1
a111 1
   const bool print = getenv("TEST_DEBUG");
@